Dystrybucja sygnału zegarowego w układach VLSI

• Autorzy: Tosik G. , Lisik Z. , Gafiout F.

Warianty tytułu

EN

Clock distribution in VLSI integrated

• Języki publikacji: PL

Abstrakty

PL

Wraz z rozwojem scalonych układów cyfrowych, o coraz większej liczbie elementów logicznych, których praca jest synchronizowana sygnałem zegarowym, właściwa dystrybucja tego sygnału na powierzchni układu scalonego staje się jednym z kluczowych zagadnień projektowania tych układów, Jest ono uważane obecnie za decydujące dla ich dalszego rozwoju. W pracy przedstawiono parametry charakteryzujące układy dystrybucji sygnału zegarowego, problemy wywołane rozbudową tych układów oraz sposoby ich rozwiązywania w cyfrowych układach VLSI. Ilustracją tych rozwiązań są układy zastosowane w procesorach IBM i DEC.

EN

The continuos development of digital ICs leading to more and more number of logic elements that proper work is synchronised by the clock signal causes that the proper distribution of the clock signal on the chip is one of the more crucial problems during such ICs design. In the paper, the parameters of clock distribution, the problems arising from more and more its complexity and the ways to cope with them are presented. It is illustrated by the newest solutions applied in IBM and DEC processors.

Słowa kluczowe

PL

układy VLSI; sygnał zegarowy; procesory IBM; procesory DEC

EN

VLSI circuits; clock signal; IBM processors; DEC processors

• Wydawca: Politechnika Łódzka, Instytut Elektroniki
• Czasopismo: Elektronika : prace naukowe
• Rocznik: 2002
• Tom: nr 7
• Strony: 23--38
• Opis fizyczny: Bibliogr. 26 poz.

Twórcy

autor

Tosik G.

• Institute of Electronics, Technical University of Łódź 18/22 Stefanowskiego Str., 90-924 Łódź, Poland tel. [phone]

autor

Lisik Z.

• Institute of Electronics, Technical University of Łódź 18/22 Stefanowskiego Str., 90-924 Łódź, Poland tel. [phone]

autor

Gafiout F.

• Institute of Electronics, Technical University of Łódź 18/22 Stefanowskiego Str., 90-924 Łódź, Poland tel. [phone]

Bibliografia

• [1] M. B. Anand H. Shibata M. Kakumu, Optimization Study of VLSI Interconnect Parameters IEEE Transaction on Electron Devices Vol.47 No.l pp. 178-186, 2000.
• [2] M. B. Anand H. Shibata M. Kakumu, Multiobjective Optimization of VLSI Interconnect Parameters, IEEE Transaction on Computer-Aided Design of Integrated Circuit and Systems Vol.17 No. 12 pp. 1252-1261, 1998.
• [3] T. N. Theis, The future of interconnection technology, IBM Journal of Research & Development Vol.44 No.3 pp.310-318, 2000.
• [4] D. Sylvester K. Keutzer, A Global Wiring Paradigm for Deep Submicron Design, IEEE Transaction on Computer-Aided Design of Integrated Circuit and Systems Vol.19 No.2 pp.242-252, 2000.
• [5] International Technology Roadmap for Semiconductors 1999 Edition.
• [6] E. Friedman, Clock Distribution Networks in VLSI Circuits and Systems, New York IEEE Press, 1995
• [7] P. E. Gronowski W. J. Bowhill R. P. Preston M. K. Gowan R. L. Allmon, High- Performance Microprocessor Design, IEEE Journal of Solid-State Circuits Vol.33 No.5 pp. 676-685, 1998.
• [8] G. E. Tellez M. Sarrafzadeh, Minimal Buffer Insertion in Clock Trees with Skew and Slave Rate Constraints, IEEE Transaction on Computer-Aided Design of Integrated Circuit and Systems Vol.16 No.4 pp.333-342 1997.
• [9] D. F Wann M. A. Franklin, Asynchronous and Clocked Control Structures for VLSI Based Interconnection Networks, IEEE Transaction on Computers Vol.32 No.3 pp.284-293 1983.
• [10] S. Sauter D. Schmitt-Landsiedel R. Thewes W. Weber, Effect of Parameter Variations at Chip and Wafer Level on Clock Skew, IEEE Transaction on Semiconductor Manufacturing Vol.13 No.4 pp. 395-400, 2000.
• [11] S. Zanella A. Nardi A. Naviani M. Quarantelli S. Saxena L. Guardiani, Analysis of the Impact of Process Variations on Clock Skew, IEEE Transaction on Semiconductor Manufacturing Vol.13 No.4 pp. 401-407, 2000
• [12] T. Soyata E. G. Eriedman, Retiming With Non-Zero Clock Skew Variable Register, and Interconnect Delay, Proc. IEEE Int’l Conf. Computer Aided Design pp. 234-241, 1994.
• [13] S. D. Kugelmass K. Steiglitz, An Upper Bound on Expected Clock Skew in Synchronous Systems, IEEE Transactions on Computers Vol.39 No.12 pp.1475-1477, 1990.
• [14] Ren-Song Tsay, An Exact Zero-Skew Clock Routing Algorithm, IEEE Transaction on Computer-Aided Design of Integrated Circuit and Systems Vol. 12 No.2 pp.242- 249, 1993.
• [15] Kaveh Azar, The historyof power dissipation, Electronics Cooling,vol.6, No.l, 2000.
• [16] A. Vittal M. Marek-Sadowska, Low-Power Buffered Clock Tree Design, IEEE Trans. Computer-Aided Design of Integrated Circuit and Systems Vol. 16 No.9 pp.965-975 1997.
• [17] D. Liu C. Svensson, Power Consumption Estimation in CMOS VLSI Circuit, IEEE J. Slid-State Circuits Vol.29 No.6 pp.663-670, 1994.
• [18] H. Kawaguchi T. Sakurai A Reduced Clock-Swing Flip-Flop (RCSFF) for 63% Power Reduction IEEE Journal of Solid-State Circuits Vol.33 No.5 pp.807-811, 1998.
• [19] Q. Zhu W. W. M. Dai, High-Speed Clock Network Sizing Optimization Based on Distributed RC and Lossy RLC Interconnect Models, IEEE Transaction on Computer-Aided Design of Integrated Circuit and Systems Vol. 15 No.9 pp. 1106-1118,1996.
• [20] R. Kay L. P. Leggi, EWA: Efficient Wiring-Sizing Algorithm for Signal Nets and Clock Nets, IEEE Transaction on Computer-Aided Design of Integrated Circuit and Systems Vol. 17 No.l pp.40-49, 1998.
• [21] A. Balboni C. Costi M. Pellenin A. Quadrini D. Sciuto, Clock Skew Reduction in ASIC Logic Design: A Methodology for Clock Tree Management, IEEE Transaction on Computer-Aided Design of Integrated Circuit and Systems Vol. 17 No.4 pp.344-356, 1998.
• [22] Daniel W. Bailey Bradley J. Benschneider, Clocking Design and Analysis for a 600 MHz Alpha Microprocessor, Jumal of Solid-State Circuits Vol.33 No.ll pp.1627-1633, 1998
• [23] R. M. Averill III K. G. Barkley M. A. Bowen P. J. Camporese A. H. Dansky R. F. Hatch D. E. Hoffman M. D. Mayo S. A. McCabe T .G. McNamara T. J. McPherson G. A. Northrop L. Sigal H. H. Smith D. A. Webber P. M. Williams, Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors, IBM J. Res. Develop. Vol.43 No5/6 pp.681-706, 1999.
• [24] H. B. Bakoglu J. T. Walker J. D. Meindl, A Symmetric Clock-Distribution Tree and Optimized High-Speed Interconnections for Reduced Clock Skew in VLSI and WSI Circuits, IEEE Int’l Conf. Computer Design pp.118-122, 1986.
• [25] D. C. Keezer V. K. Jain, Design and Evaluation of Wafer Scale Clock Distribution, Proc. IEEE Int’l Conf. Wafer-Scale Integration pp.168-175, 1992.
• [26] D. Somasekhar V. Visvanathan, A 230-MHz Half-Bit Level Pipelined Multiplier Using Single Phase Clocking, IEEE Transactions on VLSI Systems Vol. 1 No.4 pp.415-422, 1993.