Design and implementation FIR filters using FPGA

• Autorzy: Jastrzębski S.
• Języki publikacji: EN

Abstrakty

EN

Underwater acoustic channels are characterized by multipath phenomenon whose characteristics are time varying. Multipath propagation contributes to signal fading, and causes intersymbol interference (ISI) in a digital communication system. Raised cosine filters are widely used in wireless communication systems and the effects of these filters are crucial to wireless communication systems, for example underwater communication systems. Pulse shaping filters are commonly used in digital data communication systems to limit intersymbol interference. Thus, digital filters have been recognized as primary digital signal processing operation. In order to apply DSP algorithms to wireless communication systems high density Field Programmable Gate Arrays have recently emerged as ideal implementation platforms for digital filters due to its potential speed and flexibility. This paper presents the design and implementation of FIR filters using FPGA technology. The following architectures of filters are studied: multiply and accumulate (MAC) standard FIR filter, parallel transposed FIR filter, and direct-form filter using Distributed Arithmetic (DA). The proposed filters have been designed and synthesized with ISE software, and implemented with a Virtex-II FPGA device.

Słowa kluczowe

EN

FIR filters; FPGA; hydroacoustic

• Wydawca: Polskie Towarzystwo Akustyczne. Oddział Gdański
• Czasopismo: Hydroacoustics
• Rocznik: 2008
• Tom: Vol. 11
• Strony: 121--130
• Opis fizyczny: Bibliogr. 9 poz., rys., tab.

Twórcy

autor

Jastrzębski S.

• University of Technology and Life Sciences, ul. Kordeckiego 20, 85-225 Bydgoszcz, Poland,

Bibliografia

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• 2. S. Wang, B. Tang, J. Zhu, Distributed Arithmetic for FIR Filter Design on FPGA, ICCCAS 2007, pp. 620-623, 2007.
• 3. G.R. Goslin, A Guide to Using Field Programmable Gate Arrays (FPGAs) for Application-Specific Digital Signal Processing Performance, v.1.0, Xilinx, 1995.
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• 6. V. Pasham, A. Miller, K. Chapman, Transposed Form Filters, Xilinx Applicaton Note, 2001.
• 7. K. Wiatr, E. Jamro, Układy mnożące przez stały współczynnik implementowane w układach programowalnych FPGA, Kwartalnik Elektroniki i Telekomunikacji 2/2001, ss. 233-253, 2001.
• 8. K. Wiatr, E. Jamro, Implementacja szybkich układów mnożących w strukturach FPGA, Kwartalnik Elektroniki i Telekomunikacji 4/2001, ss. 495-514, 2001.
• 9. K. Chapman, Constant Coefficient Multipliers for the XC4000E, Xilinx Applicaton Note, 1996.