On application of polynominal algebra for identification of dynamic faults in interconnects

• Autorzy: Kopeć M. , Garbolino T. , Gucwa K. , Hławiczka A.
• Języki publikacji: EN

Abstrakty

EN

The paper presents a new method that is an effective instrument for investigating sources of dynamic faults in interconnects (i.e. crosstalk, delay faults, etc.). It is an extension of the previous work of the authors published in the Proceedings of the European Test Symposium 2006, where fault identification was limited to static faults only. In the proposed approach an erroneous bit sequence coming from the faulty net is reconstructed on the basis of a set of signatures. This facilitates precise identification of dynamic faults. Discussed method is applicable to interconnects between ICs mounted on the PCBs as well as interconnect networks connecting IP cores in SoCs. Moreover, it is easily scalable to any number of nets in the interconnect network and can be used with any type of test sequence and test pattern generator. There are several variant s of hardware implementation of the method. This supports finding a trade-off between area overhead and testing time.

Słowa kluczowe

EN

interconnect tests; built-in self tests; interconnect BIST; Chinese remainder theorem; fault localization; fault identification

PL

testowanie połączeń; lokalizacja uszkodzeń; identyfikacja uszkodzeń

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: Electronics and Telecommunications Quarterly
• Rocznik: 2008
• Tom: Vol. 54, No 1
• Strony: 29--41
• Opis fizyczny: Bibliogr. 13 poz., rys.

Twórcy

autor

Kopeć M.

autor

Garbolino T.

autor

Gucwa K.

autor

Hławiczka A.

• Silesian University of Technology,

Bibliografia

• 1. A. Attarha, M. Nourani: "Testing Interconnects for Noise and Skew in Gigahertz SoC", Proc. of Int. Test Conf., 2001, pp. 305-314.
• 2. A. Jutman: "At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults", Proc. of ETS'04, pp. 2-7.
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• 4. W. Yuejian, Saman M. I. Adham: Scan-Based BIST Fault Diagnosis, IEEE Trans, on CAD, Vol. 18, No. 2, 1999, pp. 203-211.
• 5. N. Koblitz: "A Course in Number Theory and Cryptography", Springer-Verlag, New York, 1994.
• 6. M. Kopeć, T. Garbolino, K. Gucwa, A. Hławiczka: "Test-per-clock detection, localization and identification of interconnect faults", Proc. ETS 2006, pp. 233-238.
• 7. T. Garbolino, M. Kopeć, K. Gucwa, A. Hławiczka: "Detection, Localisation and Identification of Interconnection Fault Using MISR Compactor", Proc. DDECS 2006, pp. 230-231.
• 8. A. Hławiczka, K. Gucwa, T. Garbolino, M. Kopeć: "Can a D flip-flop based MISR compactor reliably detect interconnect faults?" Proc. DDECS 2005, pp. 2-8.
• 9. W. Rajski, J. Rajski: "Modular Compactor of Test Responses", pp. 242-251, 24th IEEE VLSI Test Symposium, 2006.
• 10. V. Shoup: NTL: A Library fordoing Number Theory, version 5.4. http://shoup.net/ntl/.
• 11. M. Cuviello, S. Dey, X. Bai, Y. Zhao: Fault Modeling and Simulation for Crosstalk in System-On-Chip Interconnects. Proceedings of the International Conference on Computer-Aided Design (ICCAD), pp. 297-303, 1999.
• 12. X. Aragones, J. L. Gonzalez, F. Moll, A. Rubio: "Noise Generation and Coupling Mechanisms in Deep-Submicron ICs", IEEE Design & Test Computers, vol. 19, no. 5, pp. 27-35, September-October 2002.
• 13. K. Shu-Min Li, Chung Len Lee, Chauchin Su, Jwu E. Chen: "A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI", pp. 145-150, 13th Asian Test Symposium (ATS'04), 2004.