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Investigation of substrate noise coupling and isolation characteristics for a 0,35 μm HV CMOS technology

Wybrane pełne teksty z tego czasopisma
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Języki publikacji
EN
Abstrakty
EN
This paper presents the characterization of substrate noise coupling and the isolation capability of ohmic substrate contacts in a HV CMOS technology. Layout variations of contact sizes, distances, and several p+ guard structures are subject of this research. Metal shielded DUT fixtures have been developed to improve the reliability and accuracy of the measurements. All test cases are fabricated with a 0.35 μm HV CMOS technology (Vmax <= 120V). This process features high resistive native substrate (20 Ohm.cm) together with a 0.5 Ohm.cm pwell. The modeling section describes the distributed substrate "resistor" and the DUT fixture behavior.
Rocznik
Strony
379--388
Opis fizyczny
Bibliogr. 13 poz., rys.
Twórcy
autor
Bibliografia
  • 1. X. Aragones, et. al.: Substrate Coupling Trends in Future CMOS Technologies, Departament d'Enginyeria Electronica, Barcelona.
  • 2. W. Steiner: Reducing Substrate Coupling in 10 to 40 Gbit/s High-Gain Broadband Amplifiers, Ruhr-University Bochum, Germany.
  • 3. P. Basedau, Q. Huang: A Post Processing Method for Reducing Substrate Coupling in Mixed-Signal Integrated Circuits, Integrated Systems Laboratory, Swiss Federal Institute of Technology, Zurich, Switzerland.
  • 4. M. Pfost: An Experimental Study on Substrate Coupling in Bipolar/BiCMOS Technologies, IEEE Journal of Solid-State Circuits, Vol. 39, No. 10, October 2004 s. 1755.
  • 5. V. Liberali: Reducing the Coupling to the Substrate in High-Speed Data Converters, ESD-MSD Course on CMOS Data Converters for Communications Bellaterra, Barcelona (Spain) - May 10, 2002.
  • 6. S. M. Sinaga, et al.: Modeling and Analysis of Substrate Coupling in Silicon Integrated Circuits, Delft University of Technology, ECTM/DIMES.
  • 7. T. Blalack, et al.: On-chip RFIsolation Techniques, BCTM 21.1, Oct. 1, 2002.
  • 8. F. Sischka: Handling Silicon substrate effects in EM simulators, presentation from AGILENT.
  • 9. Ch. Xu, et al.: High Frequency Lumped Element Models for Substrate Noise Coupling, School of EECS, Oregon State University, Corvallis, OR 97331.
  • 10. E. G. Friedman: On-Chip Interconnect: The Past, Present, and Future, 1st NoC Workshop - DATE'06 March 10, 2006.
  • 11. W. Hoelzl: Modellierung von MOS Transistoren fur die SPICE-Simulation von Analogen, Integrierten Schaltkreisen, Master's Thesys, Techn. Univ. Graz, 1988.
  • 12. G. Murata, K. Kundert: A Substrate Modeling Methodology, www.designers-guide.org
  • 13. R. M. Vinella, et al.: Substrate Noise Isolation Experiments in a 0.18 um 1P6M Triple-well CMOS Process on a Lightly Doped Substrate", IMTC 07.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BWAH-0012-0009
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