A low-power strategy for Delta-Sigma modulators

• Autorzy: Pesenti S. , Stefanovic D. , Clement P. , Kayal M.
• Języki publikacji: EN

Abstrakty

EN

This paper presents a hybrid continuous-discrete-time Delta-Sigma modulator for portable communication systems following a low-power strategy. The proposed design methodology is extendable to different specifications. A multi-bit technique has been introduced in an efficient manner to optimize the power consumption, and an adaptive algorithm is used to allow a 3-fold reduction in the number of comparators.

Słowa kluczowe

EN

hybrid delta-sigma modulator; auto-ranging algorithm; multi-bit feedback; mismatch shaping encoder

PL

algorytm; sprzężenie zwrotne; kodowanie

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: Electronics and Telecommunications Quarterly
• Rocznik: 2007
• Tom: Vol. 53, No 4
• Strony: 361--377
• Opis fizyczny: Bibliogr. 15 poz., rys., tab., wykr.

Twórcy

autor

Pesenti S.

autor

Stefanovic D.

autor

Clement P.

autor

Kayal M.

• Marvell Semiconductor, Route de Pallates 17, 1163 Etoy, Swtzerland,

Bibliografia

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• 2. C. Zierhofer: Adaptive Sigma-Delta modulation with one-bit quantization. IEEE Trans. on circuits and systems, May 2000, pp. 408-415.
• 3. L. Dorrer, and al.: A 3-mW74-dB SNR 2-MHz continuous-time Delta-Sigma ADC with a tracking ADC quantizer in 0.13-um CMOS. IEEE J. of Solid-State Circuits, vol. 37, December 2002, pp. 1636-1644.
• 4. S. Pesenti, P. Clement, M. Kayal: Reducing the number of comparators in multi-bit Delta-Sigma modulators, IEEE Transactions on Circuits and Systems II, accepted for publication.
• 5. A. Fishov, E. Siracusa, J. Welz, E. Fogleman, I. Galton: Segmented mismatch-shaping D/A conversion. Proc. Of the IEEE International Symposium on Circuits and Systems, vol. 4, May 2002, pp. 679-682.
• 6. S. Yan, S. Sanchez: A continuous-time Sigma-Delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth. IEEE J. of Solid-State Circuits, vol. 39, January 2004, pp. 75-86.
• 7. M. Kappes: A 2.2-mW CMOS band-pass continuous-time multi-bit Delta-Sigma ADC with 68 dB of dynamic range and 1 MHz bandwidth for wireless applications. IEEE J. of Solid-State Circuits, vol. 38, July 2003, pp. 1098-1104.
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• 9. K. Nguyen, R. Adams, K. Sweetland, H. Chen: A 106-dB SNR hybrid Over-sampling analog-to-digital converter for digital audio. IEEE J. of Solid-State Circuits, vol. 40, December 2005, pp. 2408-2414.
• 10. P. Morrow, M. Chamarro, C. Lyden, P. Ventura, A. Abo, A. Matamura, M. Keane, R. O'Brien, P. Minogue, J. Mansson, N. McGuinness, M. McGranaghan, I. Ryan: A 0.18 umn 102 dB-SNR mixed CT SC audio-band Delta-Sigma ADC. IEEE International Solid-State Circuit Conference, 2005, pp. 178-179.
• 11. S. Haykin, B. van Veen: Signals and Systems. John Wiley & Sons Inc., New-York, 1999.
• 12. S. Pesenti: Hybrid continuous-discrete-time multi-bit Delta-Sigma A/D converters with auto-ranging algorithm. PhD dissertation, EPFL, Lausanne, accepted by the jury, to be published in 2008.
• 13. M. Pastre, M. Kayal: Methodology for the digital calibration of analog circuits and systems with case studies. Springer, Berlin, 2006.
• 14. M. Kayal, M. Past re: Automatic Calibration of Hall Sensor Microsystems. Microelectronics Journal.
• 15. M. Pastre, M. Kayal, H. Blanchard: Continuously gain-calibrated Hall sensor analog front-end for current measurement. International Solid-State Circuits Conference (ISSCC), February 6 to 10-San Francisco-USA.