Synthesis of Macro Petri Nets into FPGA with Distributed Memories

• Autorzy: Bukowiec A. , Adamski M.
• Języki publikacji: EN

Abstrakty

EN

In this paper a new method of Petri net array-based synthesis is proposed. The method is based on decomposition of colored interpreted macro Petri net into state machine subnets. Each state machine subnet is determined by one color. During the decomposition process macroplaces are expanded or replaced by doublers of macroplace. Such decomposition leads to parallel implementation of a digital system. The structured encoding of places is done by using minimal numbers of bits. Colored microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. Such an approach allows balanced usage of different kinds of resources available in modern FPGAs.

Słowa kluczowe

EN

decomposition; FGPAs; logic synthesis; Petri nets

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2012
• Tom: Vol. 58, No. 4
• Strony: 403--410
• Opis fizyczny: Bibliogr. 33 poz.

Twórcy

autor

Bukowiec A.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

autor

Adamski M.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

Bibliografia

• [1] M. Węgrzyn, P. Wolański, M. Adamski, and J. Monteiro, „Coloured Petri net model of application specific logic controller programs”, in Proceedings of IEEE International Symposium on Industrial Electronics ISIE'97, vol. 1. Guimaraes, Portugal: Piscataway, 1997, pp. 158-163.
• [2] M. Adamski, „Application specific logic controllers for safety critical systems”, in 14th World Congress of IFAC International Federation of Automatic Control, vol. Q: Transportation Systems: Computer Control, Beijing, China: Oxford, International Federation of Automatic Control, 1999, pp. 519-524.
• [3] D. Drusinsky and D. Harel, „Using statecharts for hardware description and synthesis”, IEEE Transactions on Computer-Aided Design, vol. 8, no. 7, pp. 798-807, 1989.
• [4] G. Łabiak, „From UML statecharts to FPGA - the HiCoS approach”, in Proceedings of the Forum on Specification & Design Languages FDL'03, Frankfurt, Germany: ECSI, 2003, pp. 354-363.
• [5] M. Doligalski, Behavioral Specification Diversification of Reconfigurable Logic Controllers, ser. Lecture Notes in Control and Computer Science. Zielona Góra : University of Zielona Góra Press, 2012, vol. 20.
• [6] T. Murata, „Petri nets: Properties, analysis and applications”, Proceedings of the IEEE, vol. 77, no. 4, pp. 541-580, 1989. [Online]. Available: http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=24143.
• [7] A. Karatkevich, Dynamic Analysis of Petri Net-Based Discrete Systems, ser. Lecture Notes in Control and Information Sciences. Berlin : Springer-Verlag, 2007, vol. 356, DOI: 10.1007/978-3-540-71560-3.
• [8] J. Esparza and M. Silva, „On the analysis and synthesis of free choice systems”, in Advances in Petri Nets 1990, ser. Lecture Notes in Computer Science, G. Rozenberg, Ed. Berlin/Heidelberg : Springer-Verlag, 1991, vol. 483, pp. 243-286.
• [9] K. Barkaoui and M. Minoux, „A polynomial-time graph algorithm to decide liveness of some basic classes of bounded Petri nets”, in Application and Theory of Petri Nets, ser. Lecture Notes in Computer Science, K. Jensen, Ed. Berlin/Heidelberg : Springer, 1992, vol. 616, pp. 62-75, DOI: 10.1007/3-540-55676-1 4.
• [10] A. Karatkevich and T. Gratkowski, „Analysis of the operational Petri nets by a distributed system”, in Proceedings of the International Conference on Modern Problems of Radio Engineering, Telecommunications and Computer Science TCSET'04, Lviv Polytechnic National University. Lviv, Ukraine: Lviv, Publishing House of Lviv Polytechnic, 2004, pp. 319-322.
• [11] A. Węgrzyn, „Parallel algorithm for computation of deadlocks and traps in Petri nets”, in 10th IEEE International Conference Emering Technologies and Factory Automation ETFA'05, vol. 1, Universita di Catania. Catania, Italy : Piscataway, IEEE Operation Center, 2005, pp. 143-148.
• [12] M. Adamski, „Petri nets in ASIC design”, Applied Mathematics and Computer Science, vol. 3, no. 1, pp. 169-179, 1993.
• [13] K. Biliński, M. Adamski, J. Saul, and E. Dagless, „Petri-net-based algorithms for parallel-controller synthesis”, IEEE Proceedings : Computers and Digital Techniques, vol. 141, no. 6, pp. 405-412, 1994.
• [14] L. Gomes, A. Costa, J. Barros, and P. Lima, „From Petri net models to VHDL implementation of digital controllers”, in 33rd Annual Conference of the IEEE Industrial Electronics Society IECON'07, Taipei, Taiwan : IEEE, 2007, pp. 94-99.
• [15] M. Węgrzyn and A. Węgrzyn, „Penlogic - system for concurrent logic controllers design”, in Design of Digital Systems and Devices, ser. Lecture Notes in Electrical Engineering, M. Adamski, A. Barkalov, and M. Węgrzyn, Eds. Berlin : Springer-Verlag, 2011, vol. 79, pp. 215-228.
• [16] M. Adamski and M. Węgrzyn, „Petri nets mapping into reconfigurable logic controllers”, Electronics and Telecommunications Quarterly, vol. 55, no. 2, pp. 157-182, 2009.
• [17] T. Łuba, M. Rawski, and Z. Jachna, „Functional decomposition as a universal method of logic synthesis for digital circuits”, in Proceedings of the 9th International Conference Mixed Design of Integrated Circuits and Systems MixDes'02, Wrocław, Poland, 2002, pp. 285-290.
• [18] A. Bukowiec and A. Barkalov, „Structural decomposition of finite state machines”, Electronics and Telecommunications Quarterly, vol. 55, no. 2, pp. 243-267, 2009.
• [19] A. Bukowiec, Synthesis of Finite State Machines for FPGA devices based on Architectural Decomposition, ser. Lecture Notes in Control and Computer Science, Zielona Góra : University of Zielona Góra Press, 2009, vol. 13.
• [20] K. Jensen, K. Kristensen, and L. Wells, „Coloured Petri nets and CPN tools for modelling and validation of concurrent systems”, International Journal on Software Tools for Technology Transfer (STTT), vol. 9, no. 3, pp. 213-254, 2007.
• [21] M. Adamski and J. Tkacz, „Formal reasoning in logic design of reconfigurable controllers”, in Proceedings of 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems PDeS'12, Brno, Czech Republic, 2012, pp. 1-6.
• [22] T. Kozłowski, E. Dagless, J. Saul, M. Adamski, and J. Szajna, „Parallel controller synthesis using Petri nets”, IEEE Proceedings - Computers and Digital Techniques, vol. 142, no. 4, pp. 263-271, 1995.
• [23] A. Węgrzyn, „On decomposition of Petri net by means of coloring”, in Proceedings of IEEE East-West Design & Test Workshop EWDTW'06, Sochi, Russia, 2006, pp. 407-413.
• [24] J. Tkacz, „State machine type colouring of Petri net by means of using a symbolic deduction method”, Measurement Automation and Monitoring, vol. 53, no. 5, pp. 120-122, 2007.
• [25] A. Karatkevich, „On macroplaces in Petri nets”, in Proceedings of IEEE East-West Design & Test Symposium EWDTS'08. Lviv, Ukraine: IEEE, 2008, pp. 418-422.
• [26] A. Bukowiec and M. Adamski, „Synthesis of Petri nets into FPGA with operation flexible memories”, in Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS'12, Tallinn, Estonia, 2012, pp. 16-21, DOI: 10.1109/DDECS.2012.6219016.
• [27] K. Skahill, VHDL for Programmable Logic. Redwood City: Addison-Wesley Publishing, 1996.
• [28] L. Gniewek and J. Kluska, „Hardware implementation of fuzzy Petri net as a controller”, IEEE Transactions on Systems, Man, and Cybernetics - Part B: Cybernetics, vol. 34, no. 3, pp. 1315-1324, 2004.
• [29] G. Łabiak, M. Adamski, M. Doligalski, J. Tkacz, and A. Bukowiec, „UML modelling in rigorous design methodology for discrete controllers”, International Journal of Electronics and Telecommunications, vol. 58, no. 1, pp. 27-34, 2012, DOI: 10.2478/v10177-012-0004-8.
• [30] G. Borowik, M. Rawski, G. Łabiak, A. Bukowiec, and H. Selvaraj, „Efficient logic controller design”, in Fifth International Conference on Broadband and Biomedical Communications IB2Com'10, Malaga, Spain, 2010, pp. [CD-ROM].
• [31] M. Doligalski, „Behavioral specification of the logic controllers by means of the hierarchical configurable Petri nets”, in Proceedings of 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems PDeS'12, Brno, Czech Republic, 2012, pp. 80-83.
• [32] A. Barkalov and L. Titarenko, Logic Synthesis for FSM-based Control Units, ser. Lecture Notes in Electrical Engineering. Berlin : Springer-Verlag, 2009, vol. 53.
• [33] E. Pastor and J. Cortadella, „Efficient encoding schemes for symbolic analysis of Petri nets”, in Proceedings of the Conference on Design, Automation and Test in Europe DATE'98. Paris, France : IEEE Computer Society Press, 1998, pp. 790-795.