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Hierarchical Configurable Petri Net Modeling in VHDL

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Języki publikacji
EN
Abstrakty
EN
The paper presents method for hierarchical configurable Petri nets description in VHDL language. Dual model is an alternative way for behavioral description of the discrete control process. Dual model consists of two correlated models: UML state machine diagram and hierarchical configurable Petri net (HCfgPN). HCfgPN are Petri nets variant with direct support of exceptions handling mechanism. Logical synthesis of dual model is realized by the description of HCfgPN model by means of hardware description language. The paper presents placesoriented method for HCfgPN description in VHDL language.
Twórcy
  • Computer Engineering & Electronics Department, University of Zielona Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland
autor
  • Computer Engineering & Electronics Department, University of Zielona Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland
Bibliografia
  • [1] G. Łabiak, M. Adamski, M. Doligalski, J. Tkacz, and A. Bukowiec, „UML modelling in rigorous design methodology for discrete controllers”, International Journal of Electronics and Telecommunications, vol. 58, no. 1, pp. 27-34, 2012.
  • [2] M. Doligalski, Behavioral specification diversification of reconfigurable logic controllers, ser. Lecture Notes in Control and Computer Science. Zielona Góra : University of Zielona Góra Press, 2012, vol. 20.
  • [3] M. Doligalski, „Behavioral specification of the logic controllers by means of the hierarchical configurable petri nets”, in Proceedings of 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems - PDeS 2012. Brno, Czechy: Brno, 2012, pp. 80-83.
  • [4] M. Adamski and J. Tkacz, „Formal reasoning in logic design of reconfigurable controllers”, in Proceedings of 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems PDeS'12, Brno, Czech Republic, 2012.
  • [5] A. Bukowiec, „Synthesis of FSMs based on architectural decomposition with joined multiple encoding”, International Journal of Electronics and Telecommunications, vol. 58, no. 1, pp. 35-41, 2012, DOI: 10.2478/v10177-012-0005-7.
  • [6] A. Bukowiec and M. Adamski, „Synthesis of Petri nets into FPGA with operation flexible memories”, in Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS'12, Tallinn, Estonia, 2012, pp. 16-21.
  • [7] A. Salihbegovic, Z. Cico, V. Marinkovi, and E. Karavdi, „Software engineering approach in the design and development of the industrial automation systems”, in the 2008 International Workshop on Software Engineering in East and South Europe, ser. SEESE'08. New York, NY, USA : ACM, 2008, pp. 15-22.
  • [8] T. Kropf, Intro. to Formal Hardware Verification. Berlin: Springer-Verlag, 1999.
  • [9] J. Tkacz, „Deadlocks detection in logic controllers by means of using gentzen reasoning method (in Polish)”, Measurement Automation and Monitoring, vol. 6, no. 6, pp. 11-13, 2006.
  • [10] E. Hrynkiewicz, A. Milik, and J. Mocha, „Dynamically reconfigurable concurrent implementation of the binary control (in Polish)”, Electronics: Constructions, Technologies, Applications, vol. 49,(11), pp. 187-190, 2008.
  • [11] M. Adamski, „Specification and synthesis of petri net based reprogrammable logic controller”, in Programmable Devices and Systems 2001 (PDS 2001) : a Proceedings Volume From The 5th IFAC Workshop, W. Ciazynski, E. Hrynkiewicz, and P. Klosowski, Eds. London : Pergamon, 2001, pp. 95-100.
  • [12] G. Łabiak and G. Borowik, „Statechart-based controllers synthesis in FPGA structures with embedded array blocks”, International Journal of Electronics and Telecommunications, vol. 56, no. 1, pp. 13-24, 2010, DOI: 10.2478/v10177-010-0002-7.
  • [13] M. Adamski and J. Tkacz, „Formal reasoning in logic design of reconfigurable controllers”, in Proceedings of 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems : PDeS 2012, Brno, 2012.
  • [14] J. Fernandes, M. Adamski, and A. Proena, „Vhdl generation from hierarchical petri net specifications of parallel controllers”, IEEE Proceedings : Computers and Digital Techniques, vol. 144, no. no 2, pp. 127-137, 1997.
  • [15] M. Adamski, M. Węgrzyn, and P. Wolański, „A vhdl based approach to logic controllers design”, in International Conference Programmable Devices and Systems : PDS'98 : Conference Proceedings, Institute of Elektronics, Silesian Technical University - Gliwice, Departament of Measurement and Control - Technical University Ostrava, Polish Section IEEE. Gliwice, Polska: Gliwice, Silesian University of Technology, 1998, pp. 9-16.
  • [16] M. Adamski and M. Węgrzyn, „Petri nets mapping into reconfigurable logic controllers”, Electronics and Telecommunications Quarterly, vol. 55, no. 2, pp. 157-182, 2009.
  • [17] P. Wolański, „Modeling digital circuits at the rtl level using a subset of petri nets and vhdl (in Polish)”, Ph. D. dissertation, Warsaw University of Technology, Faculty of Electronics and Information Technology, 1998, supervisor: Prof. dr hab. inż. Marian Adamski.
  • [18] M. Węgrzyn, „Hierarchical implementation of digital concurrent controllers using FPGA (in Polish)”, Ph. D. dissertation, Warsaw University of Technology, Faculty of Electronics and Information Technology, 1998, supervisor: dr hab. inż. Marian Adamski.
  • [19] M. Puczyńska, G. Łabiak, and P. Wolański, „Program implementation of the conversion of petri nets into vhdl (in Polish)”, in Reprogramowalne Układy Cyfrowe - RUC 2000 : Materiały III Krajowej Konferencji Naukowej, Szczecin, Polska: Szczecin, Publishing and Printing Technical University Faculty of Computer Science, 2000, pp. 285-291.
  • [20] M. Bolton, Prace Naukowe Instytutu Cybernetyki Technicznej Politechniki Wrocławskiej, 1991, ch. VHDL and its Use in VLSI Design, pp. 149-158.
  • [21] G. Bazydło and M. Adamski, „Exception handling in UML state machine implemented in digital microsystems (in Polish)”, Measurement Automation and Monitoring, vol. 56, no. 7, pp. 728-731, 2010.
  • [22] M. Adamski and G. Bazydło, „Modeling emergency situations in a hierarchical state machine UML 2.4 with the use of the attribute history (in Polish)”, in Design, Analysis and Implementation of Real-Time Systems, L. Trybus and S. Samolej, Eds., Warszawa, 2011.
  • [23] M. Doligalski and M. Adamski, „Exception handling mechanism and controll resumption in hierarchical petri nets (in Polish)”, Measurement Automation and Monitoring, vol. 57, no. 6, pp. 671-674, 2011.
  • [24] A. Karatkevich, Dynamic Analysis of Petri Net-based Discrete systems, ser. Lecture Notes in Control and Information Sciences. Berlin : Springer-Verlag, 2007, vol. 356.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BWAD-0032-0014
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