Hardware Accelerated Simulation of Crest Factor Reduction Block for Mobile Telecommunications

• Autorzy: Nikodem M. , Kępa K.
• Języki publikacji: EN

Abstrakty

EN

This paper reports results of the hardware accelerated simulations of the crest factor reduction (CFR) block which is a common element of the radio signal processing path in base stations for mobile telecommunications. Presented approach increases productivity of radio system architects by shortening the time of model architecture evaluation. This enables unprecedented scale of CFR parameter optimization which requires thousands of simulation runs. We use FPGA device and Xilinx System Generator for DSP technology in order to model CFR block in MATLAB/Simulink environment, implement the accelerator and use it for mixed hardware-software simulation. Reported approach reduces simulation time by 70%, provides straight forward use of fixed-point arithmetic and lowers power consumption by 73% at the cost of constant and relatively low overhead on model development.

Słowa kluczowe

EN

crest factor reduction; configurable hardware; hardware acceleration; FPGA; telecommunications

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2012
• Tom: Vol. 58, No. 4
• Strony: 363--368
• Opis fizyczny: Bibliogr. 11 poz., tab., wykr.

Twórcy

autor

Nikodem M.

• Institute of Computer Engineering, Control and Robotics, Wrocław University of Technology, Wybrzeże Wyspiańskiego 27, 50-370 Wrocław, Poland

autor

Kępa K.

• Virginia Bioinformatics Institute, Virginia Tech., Blacksburg, VA, USA

Bibliografia

• [1] „3rd generation partnership project : technical specification group radio access network : E-UTRA, UTRA and GSM/EDGE; multi-standard radio (MSR) base station (BS) radio transmission and reception”, 3rd Generation Partnership Project, Tech. Rep. version 11.0.0, release 11, March 2012.
• [2] O. Vaananen, J. Vankka, and K. Halonen, „Reducing the peak to average ratio of multicarrier GSM and EDGE signals”, The 13th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, vol. 1, pp. 115-119, 2002.
• [3] O. Vaananen, J. Vankka, and K. Halonen, „Simple algorithm for peak windowing and its application in GSM, EDGE and WCDMA systems”, Communications, IEEE Proceedings, vol. 152, no. 3, pp. 357-362, 2005, DOI: 10.1049/ip-com:20059014.
• [4] P. Swaroop and K. Gard, „Crest factor reduction through in-band and out-of-band distortion optimization”, in Radio and Wireless Symposium, 2008 IEEE, jan. 2008, pp. 759-762, DOI: 10.1109/RWS.2008.4463603.
• [5] C. Zhao, „Distortion-based crest factor reduction algorithms in multicarrier transmission systems”, Ph.D. dissertation, Grorgia Institute of Technology, 2007.
• [6] V. Lin, R. Speelman, C. Daniels, E. Grayver, and P. Dafesh, „Hardware accelerated simulation tool (HAST)”, in Aerospace Conference, 2005 IEEE, march 2005, pp. 1475-1483, DOI: 10.1109/AERO.2005.1559437.
• [7] T. Suh and H.-h. S. Lee, „Initial Observations of Hardware/Software Co-Simulation using FPGA”, in Architecture Research, 2nd Workshop on Architecture Research using FPGA Platforms, 2006, DOI: 10.1.1.84.3965.
• [8] R. Zoss, A. Habegger, V. Bandi, J. Goette, and M. Jacomet, „Comparing signal processing hardware-synthesis methods based on the Matlab tool-chain”, in Electronic Design, Test and Application (DELTA), 2011 Sixth IEEE International Symposium on, jan. 2011, pp. 281-286, DOI: 10.1109/DELTA.2011.58.
• [9] M. Chugh, D. Bhatia, and P. T. Balsara, „Design and implementation of configurable W-CDMA rake receiver architectures on FPGA”, Parallel and Distributed Processing Symposium, International, vol. 4, p. 145b, 2005, DOI: 10.1109/IPDPS.2005.162.
• [10] „DSP builder handbook : volume 2: DSP builder standard blockset”, Altera Corporation, Tech. Rep. 12.0, June 2012.
• [11] „System Generator for Digital Signal Processing : User Guide”, Xilinx Inc., Tech. Rep. 14.1, April 2012.