Modeling the Arithmetic Decomposition of DA-LUT Block for Heterogeneous FPGA Structures

• Autorzy: Staworko M. , Rawski M.
• Języki publikacji: EN

Abstrakty

EN

Distributed arithmetic is well known technique of designing FIR filters in FPGA devices. The quality of such filter implementation strongly depends on synthesis results of the DALUT block. Heterogeneity of modern FPGA structures introduces new possibilities into implementation process, that may lead to better results, but also makes it more complicated. This paper presents the simple mathematical model for estimating the necessary FPGA resources to implement DA-LUT using decomposition-based approach. The model takes into account the type of logic cells or memory blocks used for decomposition process. The proposed model is help ful to determinate the DALUT decomposition strategy for further automation of modified distributed arithmetic decomposition method.

Słowa kluczowe

EN

distributed arithmetic; FPGA; FIR filter; heterogeneous programmable structures

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2012
• Tom: Vol. 58, No. 4
• Strony: 335--344
• Opis fizyczny: Bibliogr. 35 poz., tab., wykr.

Twórcy

autor

Staworko M.

• Institute of Telecommunications, Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warsaw, Poland

autor

Rawski M.

• Institute of Telecommunications, Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warsaw, Poland

Bibliografia

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