Tytuł artykułu
Autorzy
Identyfikatory
Warianty tytułu
Diagnostyka analogowych układów elektronicznych z uwzględnieniem tolerancji
Konferencja
Mixed Design of Integrated Circuits and Systems MIXDES 2011 (18 ; 16-18.06.2011 ; Gliwice, Poland)
Języki publikacji
Abstrakty
This paper presents analysis of components tolerance influence on fault diagnosis efficiency of analog electronic circuits. There has been proposed method of finding optimal frequency of input periodic excitation with simultaneous maximization of components tolerances in order to keep assumed level of diagnosis efficiency. There has been also proposed departure from classical "location after detection" schema. Combination of detection and location in a single step can remarkably shorten diagnosis time. The optimization process involves genetic algorithm.
W pracy przeanalizowano wpływ tolerancji projektowych elementów na skuteczność diagnostyki analogowych układów elektronicznych. Zaproponowano metodę doboru częstotliwości okresowego pobudzenia testowego z jednoczesną maksymalizacją tolerancji elementów przy zachowaniu założonej skuteczności diagnostyki. Zaproponowano także odejście od klasycznego dwuetapowego schematu: ''lokalizacja po detekcji", co pozwoliło na skrócenie całkowitego czasu testowania. W procesie optymalizacyjnym wykorzystano algorytm genetyczny.
Słowa kluczowe
Wydawca
Rocznik
Tom
Strony
42--46
Opis fizyczny
Bibliogr. 18 poz., wykr., rys.
Twórcy
autor
- Silesian University of Technology Gliwice, Faculty of Automatic Control, Electronics and Computer Science
Bibliografia
- [1] Baker K., Richardson A. M., Dorey A. P.: Mixed signal test techniques, applications and demands. IEEE Circuits. Devices, Systems, 1996, vol. 146, p. 358-365.
- [2] Balivada A., Chen J., Abraham J. A.: Analog testing with time response parameters- IEEE Design and Test of Computers, 1996, vol. 13, p. 18-25.
- [3] Bernier J. L., Merelo J. J., Ortega J., Prieto A.: Test Pattern Generation for Analog Circuits Using Neural Networks and Evolutive Algorithms. International Workshop on Artificial Neural Networks, 1995, p. 838-844.
- [4] Catelani M., Fort A., Singuaroli R.: Hard Fault diagnosis in electronic analog circuits with radial basis function networks. 2000, IMEKO Congress, p. 167.
- [5] Chruszczyk L., Rutkowski J., Grzechca D.: Finding of optimal excitation signal for testing of analog electronic circuits. International Conference on Signals and Electronic Systems, 2006, Lodz, Poland, p. 613-616.
- [6] Chruszczyk L., Rutkowski J.: Optimal excitation in fault diagnosis of analog electronic circuits. IEEE International Conference on Electronics, Circuits, and Systems, 2008, Malta.
- [7] Dai H., Souders M.: Time domain testing strategies and fault diagnosis for analog systems. 1989, IEEE Instrumentation and Measurement Technology Conference, p. 293-298.
- [8] Goldberg D. E.: Genetic Algorithms in Search, Optimization & Machine Learning. Add ison-Wesley, 1989.
- [9] Golonek T., Rutkowski J.: Genetic-Algorithm-Based Method for Optimal Analog Test Points Selection. 2007, IEEE Trans. on Cir, and Syst-II., Vol. 54, No. 2, p. 117-121.
- [10] Golonek T., Grzechca D., Rutkowski J.: Optimization of PWL Analog Testing Excitation by Means of Genetic Algorithm. International Conference on Signal and Electronic Systems. 2008, Krakow, Poland.
- [11] Grzechca D., Rutkowski J.: Creation of Analog Fault AC Dictionary based on fuzzy - neural network and output coding, European Conference on Circuit Theory and Design, 2003, Krakow, Poland.
- [12] Grzechca D., Golonek T., Rutkowski J.: Analog Fault AC Dictionary Creation - The Fuzzy Set Approach. 2006, IEEE International Symposium on Circuits and Systems. 2006, Kos, Greece, p. 5744-5747.
- [13] Grzechca D., Chruszczyk L.: Wavelet - Neural Network to Analog Paramteric Fault Circuit Location. 13th International Mixed Signals Testing Workshop and 3rd GHz/Gbps Test Workshop, 2007, Povoa de Varzim, Portugal, p. 2-6.
- [14] Huertas J. L.: Test and design for testability of analog and mixed-signal 1C: theoretical basic and pragmatical approaches. European Conference On Circuit Theory And Design, Davos, Switzerland, 1993, p. 75-156.
- [15] Kaminska B., et al.: Analog and mixed-signal benchmark circuits - first release. IEEE International Test Conference, Washington, USA, 1997.
- [16] Milne A., Taylor D., Naylor K.:Assesing and comparing fault coverage when testing analogue circuits. 1997, IEE Circuits Devices Systems, vol. 144.
- [17] Milor L., Sangiovanni-Vincentelli A. L.: Minimizing production test time to detect faults in analog circuits. IEEE CAD of Integrated CAS, 1994, vol. 13. p. 796-813.
- [18] Savir J., Guo Z.: Test Limitations of Parametric Faults In Analog Circuits. IEEE Trans. on Instrumentation and Measurement, vol. 52. no. 5, Oct. 2003.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BWAD-0026-0009