FPGA Implementation of a Numerically Controlled Oscillator with Spur Reduction

• Autorzy: Lachowicz S. , Pfleiderer H-J.
• Języki publikacji: EN

Abstrakty

EN

This paper presents a novel method of reducing the spurious signal content in a digitally synthesized sine wave at the output of a numerically controlled oscillator (NCO). The proposed method uses a linear approximation subsystem with a reduced size look-up table (LUT). Two NCO architectures are considered. Architecture 0 - which is the standard -in which the accumulator word length is longer than the LUT address word, is compared with Architecture 1, where the accumulator bits beyond the LUT address space are used for the linear approximation of the value in between the entries of the LUT. Analysis of both architectures demonstrates that the spurious free dynamic range (SFDR) in Architecture 1 equates to 12 dBc per bit of the address space of the LUT as opposed to 6 dBc for Architecture 0. The system was implemented and tested using the Xilinx Spartan 3 platform.

Słowa kluczowe

EN

numerical controlled oscillator; digital waveform synthesis; spurious free dynamic range; FPGA

PL

scylator cyfrowy; cyfrowa synteza napięć; zakres dynamiczny; FPGA

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: Electronics and Telecommunications Quarterly
• Rocznik: 2009
• Tom: Vol. 55, No 4
• Strony: 617--624
• Opis fizyczny: Bibliogr. 7 poz., wykr.

Twórcy

autor

Lachowicz S.

autor

Pfleiderer H-J.

• Edith Cowan University, Perth, Western Australia,

Bibliografia

• 1. Analog Devices: A technical tutorial on digital signal synthesis, http://www.analog.com/static/imported-files/tutorials/ 450968421DDS_Tutorial-rev12-2-99.pdf, 1999.
• 2. L. Schuchman: Dither signals and their effects on quantization noise, IEEE Trans. Commun.Technol., Vol. COM-12, pp. 162-165, Dec. 1964.
• 3. M. J. Flanagan and G. A. Zimmerman: Spur-reduced digital sinusoid synthesis, IEEE Trans. Communications, Vol. 43, No. 7, pp. 2254-2262, July 1995.
• 4. D-U. Lee, R. C. C. Cheung, W. Luk and J. D. Villasenor: Hardware implementation trade-offs of polynomial approximations and interpolations, IEEE Trans. Computers, Vol. 57, No. 5, pp. 686-701, May 2008.
• 5. Y. Song and B. Kim. Quadrature direct digital frequency synthesizers using interpolation-based angle rotation, IEEE Trans. VLSI Syst., Vol. 12, No. 7, pp. 701-710, July 2004.
• 6. S. Lachowicz and H-J. Pfleiderer: Fast evaluation of nonlinear functions using FPGAs, Proc. 4th Intl. Symposium on Electronic Design, Test and Applications DELTA 2008, Hong Kong, Jan 2008.
• 7. Xilinx (Logic Core): DDS Compiler v2.1, DS558, March 24, 2008.