A Behavioral Model for Sigma Delta Fractional PLL and Applications to Circuit Dimensioning

• Autorzy: Duarte R. , Fernandes J. R.
• Języki publikacji: EN

Abstrakty

EN

This paper presents an accurate high level model for the design of sigma-delta fractional Phase locked loop (PLL) architectures. High level models provide simulation speedups of about two orders of magnitude when compared to transistor level simulation. When compared to other models presented in the literature the proposed model has the advantage of having the frequency instead of phase as the output of the VCO. This approach greatly simplifies the implementation of the PLL blocks and results in an increase of the overall model performance. Several nonlinear phenomenons's such as cycle slipping, spurious signals and phase noise are also accurately modelled. Finally, this paper combines genetic algorithms with the proposed behavioral model to optimize the PLL parameters and reduce the impact of the sigma-delta phase noise.

Słowa kluczowe

EN

phase locked loop; RF; high level simulation of analog circuits; genetic algorithms; design automation

PL

algorytm genetyczny; układy RF; układy synchronicznej pętli fazowej; automatyzacja projektowania; układy PLL

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: Electronics and Telecommunications Quarterly
• Rocznik: 2009
• Tom: Vol. 55, No 4
• Strony: 563--575
• Opis fizyczny: Bibliogr. 11 poz., wykr.

Twórcy

autor

Duarte R.

autor

Fernandes J. R.

• INESC-ID Lisboa, Portugal / Instituto Superior Técnico - T.U. Lisbon, Portugal,

Bibliografia

• 1. I. Galton: Delta-Sigma Data Conversion in Wireless Transceivers. IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 1, January 2002.
• 2. S. E. Meninger and M. H. Perrott: A Fractional-N Frequency Synthesizer Architecture Utilizing a Mismatch Compensated PFD/DAC Structure for Reduced Quantization-Induced Phase Noise. IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, vol. 50, no. 11, November 2003.
• 3. S. Pamarti, L. Jansson and I. Galton: A Wideband 2.4-GHz Delta-Sigma Fractional-N PLL with 1-Mb/s In-Loop Modulation. IEEE Journal of Solid-State Circuits, vol. 39, no. 1, January 2004.
• 4. S. R. Norsworthy, R. Schreier, and G. C. Temes: Delta-Sigma Data Converters, Theory, Design, and Simulation. New York: IEEE Press, 1997.
• 5. E. Drucker: Model PLL Dynamics And Phase-Noise Performance. MICROWAVES & RF, FEBRUARY 2000.
• 6. K. Kundert: Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers. The Designers Guide, Copyright © August 2006, Kenneth S. Kundert - Designer's Guide Consulting, Inc.
• 7. X. Mao, Huazhong, Y. H. Wang: Behavioral Modeling and Simulation of Jitter and Phase Noise in Fractional-N PLL Frequency Synthesizer.
• 8. M. H. Perrott, M. D. Trott and Ch. G. Sodini: A Modeling Approach for Sigma Delta Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis. IEEE Journal of Solid-State Circuits, vol. 37, no. 8, August 2002.
• 9. X. Lai, Y. Wan and J. Roychowdhury: Fast PLL Simulation Using Nonlinear VCO Macromodels for Accurate Prediction of Jitter and Cycle-Slipping due. to Loop Non-idealities and SupplyNoise. ASP-DAC 2005.
• 10. R. L. Haupt, S. E. Haupt: Practical genetic algorithms 2nd ed. Wiley-Interscience publication, 2004.
• 11. Genetic Algorithm and Direct Search Toolbox TM User's Guide, The Math Works, Inc. March 2009.