Hardware architecture of a parallel system for lane detection

• Autorzy: Pankiewicz P. , Powiertowski W. , Roszak G.
• Języki publikacji: EN

Abstrakty

EN

The aim of this paper is to describe in detail the hardware implementation of the lane detection algorithm presented at 15th International Conference "Mixed Design of Integrated Circuits and Systems". During introductory research several approaches to edge and line detection were analyzed, which resulted in optimal combination for future hardware implementation. The proposed algorithm is based on the Canny edge detector and the linear Hough transform for line detection. The system was pre-developed using the Matlab environment. The next step was the synthesizable hardware description using VHDL. A wide range of testing procedures for structural and behavioral verification was designed. The presented evaluation of both hardware and software simulation, and synthesis results suggested high capabilities of designed architecture, which have been proven during real-time hardware tests of the system.

Słowa kluczowe

EN

lane detection; VHDL; Canny edge detection; Hough transform FPGA

PL

VHDL; detekcja krawędzi; wykrywanie krawędzi; transformata Hough'a

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: Electronics and Telecommunications Quarterly
• Rocznik: 2008
• Tom: Vol. 54, No 4
• Strony: 547--560
• Opis fizyczny: Bibliogr. 7 poz., il., wykr.

Twórcy

autor

Pankiewicz P.

autor

Powiertowski W.

autor

Roszak G.

• Poznań University of Technology, Poland,

Bibliografia

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• 2. D. Bishop: Fixed point package users guide, [on-line] http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/.
• 3. B. Bosi, G. Bois, Y. Savaria: Reconfigurable pipelined 2-D convolvers for fast digital signal processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7 pp. 299-308, 1999.
• 4. J. F. Canny: A computational approach to edge detection. IEEE Transactions on Pattern Analysis and Machine Intelligence, 1986.
• 5. Y. Wang, E. K. Teoh, D. Shen: Lane detection and tracking using b-snake. Image Vision Comput., 22(4) pp. 269-280, 2004.
• 6. Xilinx, Inc. FIFOs Using Virtex-II Block RAM. [on-line] http://www.xilinx.com/support.
• 7. P. Pankiewicz, W. Powiertowski, G. Roszak: VHDL Implementation of the Lane Detection Algorithm, 15th International Conference Mixed Design of Integrated Circuits and Systems, 2008.