Synteza logiczna dla struktur typu PAL wykorzystująca bufory wyjściowe

• Autorzy: Kania D.

Warianty tytułu

EN

Logic synthesis on PAL-based devices containing output buffers

• Języki publikacji: PL

Abstrakty

PL

Struktura typu PAL stanowi jądro wielu układów CPLD. Jednym z podstawowych problemów syntezy jest problem podziału układu na odpowiednie części, realizowalne w pojedyńczych blokach logicznych typu PAL zawierających określoną liczbę iloczynów. W artykule przedstawiono metodę syntezy wykorzystującą trójstanowe bufory wyjściowe, stanowiące dodatkowe zasoby wewnętrzne bloków logicznych. Opracowane algorytmy zostały zaimplementowane i wykorzystane do podziału funkcji testowych w celu realizacji na blokach logicznych typu PAL o zadanej liczbie iloczynów. Przeprowadzono również syntezę funkcji testowych dla standardowych układów PAL, a uzyskane wyniki porównano z klasyczną metodą syntezy i z wynikami opublikowanymi w literaturze.

EN

The PAL-based structure constitutes the kernel of many CPLDs. The problem of appropriate partition of the whole devices under design into suitable parts, which can be implemented as single PAL-based logic blocks containing the limited number of terms, is one of basic problems of the synthesis process. The method of logic synthesis that makes use of three-state output buffers constituting the additional internal resources of logic blocks, is presented in this paper. Developed algorithms have been implemented and used for partitioning the benchmark circuits due to realization by means of the PAL-based logic blocks with the given number of terms. Synthesis of benchmark circuits for PAL devices has also been carried out and the obtained results have been compared to classical approach and the ones published in bibliography.

Słowa kluczowe

PL

synteza logiczna; podział; dekompozycja; minimalizacja; PLD

EN

logic synthesis; partitioning; decomposition; minimization; PLD

• Wydawca: Wydawnictwo Naukowe PWN SA
• Czasopismo: Kwartalnik Elektroniki i Telekomunikacji
• Rocznik: 2002
• Tom: Vol. 48, z. 1
• Strony: 53--66
• Opis fizyczny: Bibliogr. 27 poz.

Twórcy

autor

Kania D.

• Instytut Elektroniki, Politechnika Śląska, ul. Akademicka 16, 44-101 Gliwice,

Bibliografia

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