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Bonding technologies for 3D-packaging

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Warianty tytułu
PL
Technologie bondingu dla opakowań trójwymiarowych
Języki publikacji
EN
Abstrakty
EN
Electronics System Integration by System in Package improves the performance, reduces the size, power and cost of electronic systems. Three dimensional Systems in Package are a new way for integrating functional blocks in vertical structures. This implementation leads to shorter signal and power interconnects and this results in lower propagation delay and power consumption. The paper will introduce the 3D-integration technologies and present bonding technologies for Package-on-Package (PoP) and Die-to-Wafer 3D-technologies. Results of our research group on "Highly Reliable 3D-Microsystems" in the field of reliable solder interconnections, through-silicon-via (TSV) technologies, self-alignment approaches for die stacking, die-to-die bonding by Cu/Sn solid-liquid-interdiffusion (SLID) technology and the application of Ag-nanowire arrays for anisotropic conductive adhesives will be demonstrated.
PL
Technologia Integracji Systemów Elektroniki przez metodę System w Pakiecie poprawia wydajność, zmniejsza wielkość, moc i koszt systemów elektronicznych. Trójwymiarowe Systemy w Pakiecie to nowy sposób na zintegrowanie funkcjonalnych bloków w struktury pionowe. Implementacja ta prowadzi do krótszego sygnału i mocy połączeń, a to prowadzi do zmniejszenia opóźnienia propagacji i zużycia energii. W tym artykule przedstawione zostanie wprowadzenie do tematu integracji technologii 3D i bondingu dla technologii 3D typu Package-on-Package (PoP) oraz Die-to-Wafer. Omówione zostaną wyniki dotyczące "Wysoce Niezawodnych Mikrosystemów 3D" w zakresie wiarygodnego lutowania połączeń, technologii przelotek wewnętrz krzemu (TSV), samowyrównywania stosu, bondingu die-to-die poprzez interdyfuzje Cu/Sn (SLID) oraz zastosowanie srebrnych nanorurek dla anizotropowo przewodzących klejów.
Rocznik
Strony
9--14
Opis fizyczny
Bibliogr. 30 poz., il., rys.
Twórcy
autor
autor
autor
autor
autor
  • Matthias Graf Technische Universitat Dresden, Electronics Packaging Laboratory, Dresden, Germany
Bibliografia
  • [1] Eniac: European technology platform nanoelectronics, http//:nano.sdu.dk/PDF/Nanoelectronics-SRA(2)pdf, 2005, p. 31.
  • [2] Beelen-Hendrikx C.: Trends in IC Packaging. Proceedings of 17th European Microelectronics and Packaging Conference, 2009, [28] pp. 1-8.
  • [3] Beyne E., The Rise of the 3rd Dimension for System Integration. Proceedings of 9th International Interconnect Technology Conference, 2006, pp. 1-5.
  • [4] Xie Y., Cong J., Sapatnekar S.: Three-Dimensional Integrated Circuit Design. Springer Verlag, 2010, p. 16.
  • [5] Cognetti C., The Impact of Semiconductor Packaging Technologies on System Integration An Overview. Proceedings of 35th European Solid-State Circuit Conference, 2009, pp. 23-27.
  • [6] Jiang T., Luo S.: 3D Integration - Present and Future. Proceedings 10th Electronics Packaging Technology Conference, 2008, pp. 373-378.
  • [7] Cheah B. E., Kong J., eriaman S., Ooi K. C.: A Novel Inter-Package Connection for Advanced Package-on-Package Enabling. Proceedings of the 61st Electronic Components and Technology Conference, 2011, pp. 589-594.
  • [8] Das R. N., Egitto F. D. Bonitz B., Poliks M. D. and Markovich V. R.: Package-Interposer-Package (PIP): A Breakthrough Pack-age-on-Package (PoP) Technology, Proceedings of the 61st Electronic Components and Technology Conference, 2011, pp. 619-624.
  • [9] Ho S. W. Daniel F. M., Siow L. Y., Seetoh W. H. Lee W. S., Chong S. C., Rao V. S.: Double Side Redistribution Layer Process on Embedded Wafer Level Package for Package on Package (PoP) Applications. Proceedings of the 12th Electronics Packaging Technology Conference, 2010, pp. 383-387.
  • [10] Smith L.: Package-on-package: thinner, faster, denser. Solid State Technology, Vol. 54, Issue 7, July 2011.
  • [11] Roozeboom F., Blauw M., Lamy Y., Grunsven E., Dekkers W., Verhoeven J., Heuvel E., Drift E., Kessels E., Sanden R.: Deep Reactive Ion Etching of Through Silicon Vias, in P. Garrou, C. Bower and P. Ramm, Handbook of 3D Integration. Wiley-VCH Verlag, 2008, Vol. 1.
  • [12] Vempati S. R., Ho S. W., Lee W. S. V., Li H. Y., Liao E., Ranganathan N., Chai T. C., Xiaowu Z., Pinjala D.: TSV interposer fabrication for 3D IC packaging. Proceedings of the 11th Electronics Packaging Technology Conference, 2009, pp. 431-437.
  • [13] Yoshida A., Wen S., Lin W., Kim J. and Ishibashi K., A Study on an Ultra Thin PoP using Through Mold Via Technology, Proceedings of the 61s1 Electronic Components and Technology Conference, 2011, pp. 1547-1551.
  • [14] Yoon S. W., Ishibashi K., Dzafir S., Prashant M., Marimuthu P. C., Carson F.: Development of Super Thin TSV PoP. Proceedings of the 61st Electronic Components and Technology Conference, 2011, pp. 274-278.
  • [15] Yim M. J., Strode R., Brand J., Adimula R., Zhang J. J., Yoo C.: Ultra Thin POP Top Package using Compression Mold: Its Warpage Control. Proceedings of the 61st Electronic Components and Technology Conference, 2011, pp. 1141-146.
  • [16] Pahlke S.: Beitrage zur Second-Level-Charakterisierung von 3D-Package-on Package, Diploma Thesis, Technische Universitat Dresden, 2011.
  • [17] Meier K., Roellig M., Wiese S., Wolter K.-J.: Mechanical Behaviour of Typical Lead-Free Solders at High Strain Rate Conditions. Proceedings of the 12th Electronics Packaging Technology Conference, 2010, pp. 825-831.
  • [18] International Roadmap for Semiconductors, The next Step in Assembly and Packaging: System Level Integration in the Package (SiP). ITRS White Paper, Vol. 9, 2007, pp. 5-12, pp. 103-106.
  • [19] Liu X., Chen Q., Dixit P.: Failure Mechanisms and Optimum Design for Electroplated Copper Through Silicon Vias (TSV). Proceedings of the 59th Electronic Components and Technology Conference, 2009, pp. 1-6.
  • [20] International Roadmap for Semiconductors, Assembly and Packaging. ITRS Roadmap, 2007, pp. 5-12, pp. 32-35.
  • [21] Wolf M.: High Aspect Ratio TSV Copper Filling with different Seed Layers. Proceedings of the 58th Electronic Components and Technology Conference, 2008, pp. 1-8.
  • [22] Henry D.: Development and characterization of high electrical performances TSV for 3D applications. Proceedings of the 11th Electronics Packaging Technology Conference, 2009, pp. 1-8.
  • [23] Saettler P., Meier K., Wolter K.-J.: Considering Copper Anisotropy for advanced TSV-modeling. Proceedings of the 34th International Spring Seminar on Electronics Technology, 2011, pp. 1-5.
  • [24] Agarwal R., Zhang W., Limaye P., Labie R., Dimcic B., Phommahaxay A., Soussan P.: Cu/Sn Microbumps Interconnect for 3D TSV Chip Stacking. Proceedings of the 60th Electronic Components and Technology Conference, 2010, pp. 858-863.
  • [25] Bernstein L.: Semiconductor Joining by the Solid-Liquid-Interdiffusion (SLID) Process. I. The Systems Ag-In, Au-In, and Cu-In. Journal of Electrochemical Society, Vol. 113, Issue 12, 1966, pp. 1282-1288.
  • [26] Herzog T., Wolter K.-J., Canchi Purushothama K., Manokaran V.: Investigation and Optimization of Residue-Free Plasma-Assisted Reflow Soldering of SnAgCu by DoE. Electronics Systemintegration Technology, 2006, pp. 1071-1081.
  • [27] Chai Y., Zhang K., Zhang M., Chan P. C. H., Yuen M. M F.: Carbon nanotube/copper composites for via filling and thermal management. Proceedings of the 57th Electronic Components and Technology Conference, 2007, pp. 1224-1229.
  • [28] Yi Li Yim M. J., Moon K. S., Wong C. P.: High Performance Nano-scale Conductive Films with Low Temperature Sintering for Fine Pitch Electronic Interconnect. Proceedings of the High Density Packaging and Microsystem Integration, 2007.
  • [29] Graf M., Meier K., Haehnel V., Schloerb H., Eychmueller A., Wolter K.-J.: Nanowire Filled Polymer Films for 3D System Integration. Proceedings of the 14th International Interconnect Technology Conference and Materials for Advanced Metallization Conference, 2011.
  • [30] Li A. P., Mueller F., Birner A., Nielsch K., Goesele U.: Hexagonal pore arrays with a 50-420 nm interpore distance formed by self-organization in anodic alumina. Journal of Applied Physics, Vol. 84, No. 11, 1998, pp. 6023-6026.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BWA1-0049-0021
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