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Tytuł artykułu

Statechart-based Controllers Synthesis in FPGA Structures with Embedded Array Blocks

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Języki publikacji
EN
Abstrakty
EN
Statechart diagrams, in general, are visual formalism for description of complex systems behaiour. Digital controllers, which act as reactive systems, can be very conveniently modeled with statecharts and efficiently synthesized in modern programmable devices. The paper presents in details syntax and semantics of statecharts and new implementation scheme. The issue of statecharts synthesis is not still ultimately solved. Main feature of the presented approach is the transformation of statechart diagrams into Finite State Machine, and through KISS format, functional decomposition and mapping into Embedded Memory Blocks. Embedded Memory are part of the modern programmable devices.
Twórcy
autor
autor
  • Computer Eng. & Electronics Dept., University of Zielona Góra, Podgórna 50, 65-246 Zielona Góra, Poland, G.Labiak@iie.uz.zgora.pl
Bibliografia
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  • [3] Wiśniewski R.: Syntheis of Compositional Microprogram Control Units for Programmable Devices. Zielona Góra: University of Zielona Góra Press, Poland, Nov. 2009.
  • [4] Harel D.: Statecharts: A Visual Formalism for Complex Systems, Science of Computer Programming, vol. 8, pp. 231–274, 1987.
  • [5] Unified Modeling Language Specification. Version 1.4.2. ISO/IEC 19501, Object Management Group, OMG, 250 First Avenue, Needham, MA 02494, U.S.A., Apr. 2005. [Online]. Available: http://www.omg.org/cgi-bin/doc?formal/05-04-01
  • [6] Drusinsky D., Harel D.: Using Statecharts for Hardware Description and Synthesis. IEEE Transaction on Computer-Aided Design, vol. 8, no. 7, pp. 798–807, Jul. 1989.
  • [7] Drusinsky-Yoresh D.: A State Assignment Procedure for Single-Block Implementation of State Chart. IEEE Transaction on Computer-Aided Design, vol. 10, no. 12, pp. 1569–1576, Dec. 1991.
  • [8] Ramesh S.: Efficient Translation of Statecharts to Hardware Circuits. in Proceedings of Twelfth International Conference on VLSI Design, Jan. 1999, pp. 384–389.
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  • [11] Łabiak G.: HiCoS Homepage, http://www.uz.zgora.pl/glabiak, 2004. [Online]. Available: http://www.uz.zgora.pl/glabiak
  • [12] Łabiak G. From UML statecharts to FPGA - the HiCoS approach, in Proceedings of Forum on specification & Design Languages – FDL'03, Frankfurt am Main, Sep. 2003, pp. 354–363.
  • [13] Łabiak G. From statecharts to FSM-description - transformation by means of symbolic methods. in Discrete-Event System Design - DESDes '06. A proceedings volume from the 3rd IFAC Workshop, Rydzyna n. Leszno, Oct. 2006, pp. 161–166.
  • [14] Borowik G., Falkowski B. J., Łuba T.: Cost-efficient synthesis for sequential circuits implemented using embedded memory blocks of fpga's, 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 99–104, 2007.
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  • [18] Łabiak G.: The use of hierarchical model of concurrent automaton in digital controller design, in polish, ISBN: 83-89712-42-3, ser. Prace Naukowe z Automatyki i Informatyki. Zielona Góra: Oficyna Wydawnicza Uniwersytetu Zielonogórskiego, 2005, vol. VI.
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  • [21] Łabiak G.: Symbolic States Exploration of UML Statecharts for Hardware Description, in Design of Embedded Control Systems, M. A. Adamski, A. Karatkevich, and M. Węgrzyn, Eds. Springer, 2005, pp. 73–83.
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Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BWA1-0041-0002
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