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Tytuł artykułu

Hardware-software system for acceleration of image processing operations

Autorzy
Wybrane pełne teksty z tego czasopisma
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Warianty tytułu
Konferencja
International Conference on Computer Vision and Graphics ICCVG 2006 (25-27.09.2006 ; Warsaw, Poland)
Języki publikacji
EN
Abstrakty
EN
The paper presents design and architecture of a hybrid software/hardware system for acceleration of image processing. The front end consists of a software interface that defines the basic data structures and exchange mechanisms for connecting to external software. The back end consists of a hardware board which is responsible for acceleration of image computations. Thus, the two main components follow the handle/body concept, which allows modifications to the implementation without changes in interfaces. This flexibility allows for better resource usage, and faster development, and facilitates system extensions. In this paper we present the design and implementation issues for the system, as well as discuss its run-time performance for the selected image operations.
Rocznik
Strony
329--337
Opis fizyczny
Bibliogr. 19 poz., tab., wykr., il.
Twórcy
autor
  • AGH - University of Science and Technology, Al. Mickiewicza 30, 30-059 Kraków, Poland
Bibliografia
  • [1] IEEE Standard for Binary Floating-Point Numbers, IEEE Std 754-1985, New York, 1985.
  • [2] Chrysafis A., Lansdowne S.: Motorola digital signal processors. Fractional and Integer Arithmetic Using the DSP56000 Family of General-Purpose Digital Signal Processors. Motorola Application Note APR3/D, 1993.
  • [3] Ritter G.: Image Algebra. Available at: ftp://ftp.cise.ufl.edu/pub/src/ia/documents, 1994.
  • [4] Gamma E., Helm R., Johnson R., Vlissides J.: Design Patterns. Elements of reusable object-oriented software. Addison Wesley, 1995.
  • [5] Knuth D.: The Art of Computer Programming. Vol. II. Addison Wesley, 1998.
  • [6] Gradshteyn I. S., Ryzhik I.M.: Table of Integrals, Series, and Products. 6th Ed. Academic Press, 2000.
  • [7] Alexandrescu A.: Modern C++ design. Generic Programming and Design Patterns Applied. Addison Wesley, 2001.
  • [8] Gonzalez R. C., Woods R. E.: Digital image processing. Prentice Hall, 2002.
  • [9] Kindahl M.: Implementing a fixed point arithmetic class. IAR Technical Report, 2002.
  • [10] Analog Devices: Extended-Precision Fixed-Point Arithmetic on the Blackfin Processor Platform, Technical Note EE-186, Analog Devices, 2003.
  • [11] Crookes D., Benkrid K., Bouridane A., Alotaibi K., Benkrid A.: High Level Programming for Real Time FPGA Based Image Processing. Technical Report, School of Computer Science, The Queen's University of Belfast, Belfast BT7 INN, UK, 2003.
  • [12] Draper B. A., Beveridge R., Bhm A. P. W., Ross C., Chawathe M.: Accelerated image processing on FPGAs. IEEE Tr. on Image Processing, 12(12), 1543-1551, 2003.
  • [13] Forsyth D. A., Ponce J.: Computer Vision. A modern approach. Prentice Hall, 2003.
  • [14] Vandervoorde D., Josuttis N. M.: C++ templates. Addison Wesley.
  • [15] INTEL: Intel® Open Source Computer Vision Library (www.sourceforge.net), 2004.
  • [16] Jähne B.: Digital Image Processing. Springer, 2005.
  • [17] www.pandora-int.com, 2006.
  • [18] www.research.microsoft.com/research/vision/, 2006.
  • [19] www.xilinx.com, 2006.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BWA1-0025-0010
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