Median filter implementations

• Autorzy: Caban D. , Zamojski W.
• Języki publikacji: EN

Abstrakty

EN

The paper reports on some experiments with implementing median or other rank--order digital image filters using field programmable devices. It demonstrates that a single field programmable device bay be used to build a median filter. The performance delivered using a Xilinx XC4000E-1 device exceeded 35 million pixels per second, when filtering within a 3×3 pixels window using 8-bit pixel representation. These results were obtained using autosynthesis, avoiding any direct manipulation in the design.

Słowa kluczowe

EN

median; rank--order filter; image processing; FPGA implementation

• Wydawca: Institute of Information Technology of the Warsaw University of Life Sciences – SGGW
• Czasopismo: Machine Graphics and Vision
• Rocznik: 2000
• Tom: Vol. 9, No. 3
• Strony: 719--728
• Opis fizyczny: Bibliogr. 10 poz.

Twórcy

autor

Caban D.

autor

Zamojski W.

• Institute of Engineering Cybernetics, Wrocław University of Technology