Monitoring of border trap effects in MOS capacitors by the voltage step technique

• Autorzy: Boużyk A. , Przewłocki H. M.
• Języki publikacji: EN

Abstrakty

EN

This paper deals with application of the voltage step technique, developed in [6-9], to determine border traps density distributions in MOS capacitors. Changes of these distributions, caused by the negative bias temperature stress, were also monitored using the same technique. Results obtained arc compared with results reported in [6-9] and discussed. An estimation procedure, developed in [18], of the trap density distribution in function of their distance from the Si-SiO₂ interface is outlined.

• Wydawca: Institute of Electron Technology
• Czasopismo: Electron Technology
• Rocznik: 1999
• Tom: Vol. 32, No. 4
• Strony: 396--400
• Opis fizyczny: Bibliogr. 18 poz.

Twórcy

autor

Boużyk A.

autor

Przewłocki H. M.

• Institute of Electron Technology, al. Lotników 32/46, 02-668 Warszawa, Poland