A low-power silicon bipolar integrated circuit for 2.5 Gb/s communication systems receivers with a novel topology for the transimpedance amplifier

• Autorzy: Trifiletti A. , Centurelli F. , Fiacco G. , Pallotta A.
• Konferencja: Mixed Design of Integrated Circuits and Systems. 5 International Conference MIXDES' 98 (18-20.06.1998 ; Łódź, Poland)
• Języki publikacji: EN

Abstrakty

EN

In this paper we present the design and the results of preliminary measurements of an IC that forms the electrical part of a front-end for SDH STM-16 (2.5 Gb/s) optical communication system receivers. The circuit has been designed using a 27 GHz Silicon bipolar process and integrates a trasimpedance amplifier and a loss-of-signal detector. The transimpedance amplifier is based on a novel topology that offers differential autputs and an extra gain of 6 dB for the forward path amplifier; the loss-of-signal detector also features a novel topology for the trigger function. The circuit uses a single supply voltage of 3.3 V and total power dissipations is below 135 mW. The trasimpedance amplifier has been designed to show an overall gain of 71 dB with a bandwidth in excess of 1.9 GHz, for a total input capacitance of 0.5 pF. The loss-of-signal detector thereshold level can be adjusted for an input signal ranging from 2 to 200 µA by varying an external resistor. We were able to perform preliminary measurements on the IC, and the results, when the parasitic elements are considered, are in good agreement with the simulations.

• Wydawca: Institute of Electron Technology
• Czasopismo: Electron Technology
• Rocznik: 1999
• Tom: Vol. 32, No. 3
• Strony: 277--281
• Opis fizyczny: Bibliogr. 8 poz.

Twórcy

autor

Trifiletti A.

autor

Centurelli F.

autor

Fiacco G.

autor

Pallotta A.

• Departament of Electronic Engineering, University of Rome "La Sapienza", Via Eudossiana 18, 00184 Roma, Italy,