High frequency four noise parameters of silicon-on-insulator-based technology MOSFET : prospects for application to low noise RF intergrated circuits

• Autorzy: Dambrine G. , Raskin J. P. , Picheta L. , Vanhoenacker D. , Colinge J. P. , Cappy A.
• Konferencja: Symposium "Diagnostic and Yield : SOI-Materials, Devices and Characterization" (4 ; 22-24.04.1998 ; Warsaw, Poland)
• Języki publikacji: EN

Abstrakty

EN

An exhaustive experimental study of the high frequency noise properties of MOSFET in Silicon-on-Insulator (SOI) technology is presented. Various gate geometries are fabricated to study the influence of effective channel length and gate finger width on the four noise parameters. The high level of MOSFET sensitivity to the minimum noise matching conditions is demonstrated. From experimental results, optimization ways to realize ultra low noise amplifiers are discussed. The capability of the fully depleted standard SOI CMOS process for realizing low noise amplifiers for multigigahertz portable communication systems is shown. A minimum noise figure of about 0.7 dB and an available gain of 15 dB at 2 GHz have been obtained in the case of 0.6 µm effective gate length processes for applications in upper frequency range.

• Wydawca: Institute of Electron Technology
• Czasopismo: Electron Technology
• Rocznik: 1999
• Tom: Vol. 32, No. 1/2
• Strony: 81--87
• Opis fizyczny: Bibliogr. 29 poz.

Twórcy

autor

Dambrine G.

• Departament Hyperfrequences et Semiconducteurs, I.E.M.N. Avenue Poincare, B.P. 69, F-59652 Villeneuve d'Ascq Cedex, France

autor

Raskin J. P.

autor

Picheta L.

autor

Vanhoenacker D.

autor

Colinge J. P.

autor

Cappy A.