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This paper presents a software/hardware bundle for studying, training and research related to IEEE 1149.1 Boundary Scan (BS) standard. The presented package includes a software environment Trainer 1149 that is capable to graphically visualize BS facilities and perform fine-grain simulation of BS test process. Trainer 1149 provides a cozy graphical design and simulation environment of BS-enabled chips and non-BS clusters. It provides the user with a full flexibility in working with any type of BS structures by supporting standard formats such as Boundary Scan Description Language and SVF (for defining test patterns). A special fault simulation mode allows injecting various types of interconnection faults to simulate their impact and inspect them using interactive tools. Trainer 1149 is the main component of a recent goJTAG initiative that aims at bringing JTAG tools closer to the user for both learning and experimental work purposes. The software part is implemented in multi-platform Java environment and distributed as an open-source freeware. Using a convenient low-cost USB-JTAG controller, one can also test real defects in real hardware. Such combination of features is unique for a public domain BS package.
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Tom
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233--239
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Bibliogr. 12 poz., wykr.
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autor
autor
autor
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- Testonica Lab Raja 15, 12618 Tallinn, Estonia, konstantin@testonica.com
Bibliografia
- [1] IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std. 1149.1-2001, 2001.
- [2] (2010) The International Technology Roadmap for Semiconductors, 2010 Update: Test and Test Equipment. [Online]. Available: http: //www.itrs.net/
- [3] D. Crosier, L. Purser, and H. Smidt, “Trends V: Universities Shaping the European Higher Education Area,” European University Association, p. 97, 2007.
- [4] (2011) Trainer 1149. Testonica LAB. [Online]. Available: http: //www.testonica.com/1149/
- [5] H.-D. Wuttke and K. Henke, “Teaching digital design with tool-oriented learning modules “living pictures”,” in Proc. of 32nd ASEE/IEEE Frontiers in Education Conference, vol. 3, Boston, USA, nov. 2002, pp. S4G-25 - S4G-30.
- [6] (2011) goJTAG initiative. [Online]. Available: http://www.gojtag.com/
- [7] “FT2232H dual high speed USB to multipurpose UART/FIFO IC,” data sheet FT 000061, Future Technology Devices International Limited, 2011.
- [8] (2011) JTAG Scan Educator. Texas Instruments Incorporated. [Online]. Available: http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=satb002a
- [9] (2011) JTAG/Boundary Scan Coach - interactive learning software for IEEE1149.X. GOPEL Electronic. [Online]. Available: http: //www.goepel.com/index.php?L=4&id=1418
- [10] A. Jutman, A. Peder, J. Raik, M. Tombak, and R. Ubar, “Structurally synthesized binary decision diagrams,” in Proc. of 6th International Workshop on Boolean Problems (IWSBP’04), Freiberg, Germany, 23-24 Sep. 2004, pp. 271-278.
- [11] (2011) Turbo tester. [Online]. Available: http://www.pld.ttu.ee/tt/
- [12] A. Jutman, R. Ubar, and V. Rosin, “A Software System for IEEE 1149.1 Boundary Scan Design, Simulation, and Demonstration,” in IEEE European Board Test Workshop, Tallinn, Estonia, 25-26 May 2005.
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Bibliografia
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bwmeta1.element.baztech-article-BWA0-0053-0023