A Precise and High Speed Charge-Pump PLL Model Based on SystemC/SystemC-AMS

• Autorzy: Ma K. , Van Leuken R. , Vidojkovic M. , Romme J. , Rampu S. , Pflug H. , Huang L. , Dolmans G.
• Języki publikacji: EN

Abstrakty

EN

The Phase Locked Loop (PLL) has become an important part of electrical systems. When designing a PLL, an efficient and reliable simulation platform for system evaluation is needed. However, the closed loop simulation of a PLL is time consuming. To address this problem, in this paper, a new PLL model containing both digital and analog parts based on SystemC/SystemC-AMS (BETA version) is presented. Many imperfections such as Voltage Control Oscillator (VCO) noise or reference jitter are included in this model. By comparing with the Matlab model, the SystemC/SystemC-AMS model can dramatically reduce simulation time. Also, by comparing with Analog Devices ADI SimPLL simulation results, Cadence simulation results and real measurement results, the accuracy of the SystemC/SystemC-AMS model is demonstrated. The paper shows the feasibility of a unified design environment for mixed-signal modelling based on SystemC/SystemC-AMS in order to reduce the cost and design time of electrical systems.

Słowa kluczowe

EN

SystemC/SystemC-AMS; phase locked loop; radio frequency; mixed-signal modeling; hardware description language

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2012
• Tom: Vol. 58, No. 3
• Strony: 225--232
• Opis fizyczny: Bibliogr. 6 poz., wykr.

Twórcy

autor

Ma K.

autor

Van Leuken R.

autor

Vidojkovic M.

autor

Romme J.

autor

Rampu S.

autor

Pflug H.

autor

Huang L.

autor

Dolmans G.

• Holst Centre, HTC 31, 5656 AE, Eindhoven, Netherlands,

Bibliografia

• [1] S. Huang, H. Ma, and Z. Wang, “Modeling and Simulation to the Design of Fractional-N Frequency Synthesizer,” in Design, Automation & Test in Europe Conference & Exhibition, Nice, Apr. 2007, pp. 1-6.
• [2] L. Liu, Y. Yang, Z. Zhu, and Y. Li, “Design OF PLL System Based VERILOG-AMS Behavior Models,” in VLSl Design & Video Tech, May 2005, pp. 67-70.
• [3] T. Xu, H. L. Arriens, R. van Leuken, and A. de Graaf, “A precise SystemC-AMS model for Charge Pump Phase Lock Loop with multiphase outputs,” in ASICON, Oct. 2009, pp. 1-6.
• [4] Open SystemC Initiative (10 Feb. 2010), SystemC AMS extensions User’s Guide. [Online]. Available: http://www.systemc.org/downloads/standards/
• [5] P. Harpe, C. Huang, S. Rampu, and M. Vidojkovic, “Analog BAN Radio Blocks C Designs for Oct09 and April10 Tapeouts,” Holst Centre, Netherlands, Tech. Rep. TN-10-WATS-TP2-050, Jun. 2010.
• [6] S. Bittner, S. Krone, and G. Fettweis, Tutorial on Discrete Time Phase Noise Modeling for Phase Locked Loops. [Online]. Available: http://www.vodafone-chair.com/staff/bittner/