Powiadomienia systemowe
- Sesja wygasła!
- Sesja wygasła!
Identyfikatory
Warianty tytułu
Konferencja
International Conference on System Engineering - ICSEng (21 ; 16-18.08.2011) ; Las Vegas, USA
Języki publikacji
Abstrakty
The paper presents a set of algorithms dedicated for synthesis of reconfigurable logic controllers implemented on FPGA platform and programmed according to IEC1131 and EN61131. The program is compiled to hardware structure with a massive parallel processing. The developed method automatically allocates resources and operations. It controls resource usage and operation timing. Using mixed concept of operation allocation that considers operation timing and forms combinatorial chains of operations number of execution cycles can be reduced. An example of logic functions, PID controller and mixed arithmetic and logic programming examples are considered. Introducing the automatic implementation method allows flexible implementing the control algorithms. The maximal possible parallelism (limited only by the algorithm dependencies and available resources) is introduced.
Słowa kluczowe
Rocznik
Tom
Strony
85--94
Opis fizyczny
Bibliogr. 30 poz., wykr.
Twórcy
autor
- Institute of Electronics, Silesian University of Technology, Gliwice, Poland
autor
- Institute of Electronics, Silesian University of Technology, Gliwice, Poland
Bibliografia
- [1] H. Berger, Automating with STEP 7 in LAD and FBD - SIMATIC S7-300/400 Programmable Controllers. Siemens AG., 2001.
- [2] G. Michel, Programmable Logic Controllers - Architecture and Applications. John Willey & Sons, 1992.
- [3] M. Chmiel, E. Hrynkiewicz, and A. Milik, “Concurrent operation of the processors in bit-byte CPU of a PLC,” in Proceedings of IFAC World Congress, July 2005.
- [4] M. Chmiel and E. Hrynkiewicz, “Remarks on parallel bit-byte cpu structures of programmable logic controllers,” in Design of Embedded Control Systems, M. W. Adamski M. A., A. Karatkevich, Ed. Springer Science + Business Media Inc., 2005, pp. 231–242.
- [5] M. Chmiel, E. Hrynkiewicz, and A. Milik, “Compact PLC with eventdriven program tasks execution,” in Preecedings of 3rd IFAC Workshop on Discrete Event System Design, DESDes’06, September 2006, pp. 99–104.
- [6] S. Devadas, A. Ghosh, and K. Keutzer, Logic Synthesis. McGraw-Hill Inc., 1994.
- [7] D. Gajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis. Introduction to Chip and System Design. Kluwer Academic Publishers, 1994.
- [8] A. Mishchenko. (2010) Abc: A system for sequential synthesis and verification. [Online]. Available: http://www.eecs.berkeley.edu/alanmi/abc/.
- [9] A. Milik and E. Hrynkiewicz, “PID module for reconfigurable logic controller,” in Proceedings of Programmable Devices and Systems 2000 Conf., Ostrava, Czech Rep., 2000.
- [10] A. Milik, “High level synthesis - reconfigurable hardware implementation of programmable logic controller,” in Proceedings of IFAC Workshop on Programmable Devices and Embedded Systems, February 2006.
- [11] S. Shanta and S. Dipali, “A new generation of PLC-an FPGA based PLC,” in Proceedings of the SICE Annual Conference, SICE 2005 Annual Conference in Okayama, 2005, pp. 2367–2370.
- [12] L. Yadong, Y. Kazuo, F. Makoto, and M. Masahiko, “Model-driven programmable logic controller design and FPGA-based hardware implementation,” in Proceedings of the ASME International Design Engineering Technical Conferences and Computers and Information in Engineering Conference-DETC2005, 2005, pp. 81–88.
- [13] Xilinx, DS-099, Spartan-3 FPGA Family, ver.2.1. Xilinx, 2006.
- [14] International Standard IEC 1131, Programmable Controllers, International Electronics Commission Std. IEC, Geneva, 1992.
- [15] J. Welch, “Translating unrestricted relay ladder logic into boolean form.” Computers in Industry, vol. 20, pp. 45–61, 1992.
- [16] S. Ichikawa, M. Akinaka, R. Kieda, and H. Yamamoto, “Converting PLC instruction sequence into logic circuit: A preliminary study,” in Proceedings of IEEE International Symposium on Industrial Electronics, vol. vol.4, July 2006, pp. 2930–2935.
- [17] D. Du, X. Xu, and K. Yamazaki, A study on the generation of siliconbased hardware PLC by means of the direct conversion of the ladder diagram to circuit design language. Springer London, 2010, vol. 49.
- [18] D. Du, Y. Liu, X. Guo, K. Yamazaki, and M. Fujishima, “Study on LD-VHDL conversion for FPGA-based PLC implementation,” The International Journal of Advanced Manufacturing Technology, vol. 40, pp. 1181–1190, 2009.
- [19] A. V. Aho, R. Sethi, and J. Ullman, Compilers: Principles, Techniques, and Tools. Addison-Wesley, 1986.
- [20] S. Akers, “Binary decision diagrams,” IEEE Transactions on Computers, vol. C-27, pp. 509–516, June 1978.
- [21] R. E. Bryant, “Graph based algorithms for boolean function manipulation,” IEEE Transactions on Computers, vol. C-35, pp. 677–691, August 1986.
- [22] S.-I. Minato, Binary Decision Diagrams and Applications For VLSI CAD. Kluwer Academic Publisher, 1995.
- [23] Xilinx, UG073, XtremeDSP for Virtex-4 FPGAs User Guide. Xilinx, 2007.
- [24] Xilinx, UG389, Spartan-6 FPGA DSP48A1 Slice. Xilinx, 2009.
- [25] Xilinx, DS302, Virtex-4 FPGA Data Sheet: DC and Switching Characteristics. Xilinx, 2007.
- [26] Xilinx, DS162 Spartan-6 FPGA Data Sheet: DC and Switching Characteristics. Xilinx, 2011.
- [27] G. Hachtel and F. Somenzi, Logic synthesis and verification algorithms. Springer, 1996.
- [28] S. Hassoun and T. Sasao, Logic synthesis and verification. Kluwer Academic Publisher, 2002.
- [29] A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, “Combinational and sequential mapping with priority cuts,” in Precedeenigs of Computer Aided Design Conference. IEEE, 2007, pp. 354–361.
- [30] R. J. Bibero, Microprocessors in Instruments and Control. John Willey & Sons, 1990.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BWA0-0051-0052