Petri Net Based Specification in the Design of Logic Controllers with Exception Handling Mechanism

• Autorzy: Doligalski M. , Adamski M.
• Konferencja: International Conference on System Engineering - ICSEng (21 ; 16-18.08.2011) ; Las Vegas, USA
• Języki publikacji: EN

Abstrakty

EN

Hierarchical Petri nets beside UML state machine diagrams, sequentional function charts (SFC) and hierarchical concurrent state machines are common solution for specification of logic controllers. These specification formats provide both concurrency and modeling on multi levels of abstraction (hierarchic approach). But only state machine diagrams supports exceptions handling in direct way. Program model presented in form of state machine diagram may be later transformed into a program in the SFC language or transformed in the Petri Net and implemented in the FPGA structure. Similarity between SFC language and Petri Nets give us lot of tools for analysis such control system. Article presents new approach for exceptions handling in hierarchical Petri nets as formal specification for logic controllers. Proposed method of specification can be used independently or as a part of dual specification (correlated state machine diagram and hierarchical configurable Petri Net).

Słowa kluczowe

EN

logic controller; dual specification; hierarchical Petri net; UML; state machine diagram

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2012
• Tom: Vol, 58, No. 1
• Strony: 43--48
• Opis fizyczny: Bibliogr. 8 poz., wykr.

Twórcy

autor

Doligalski M.

• Computer Engineering & Electronics Department, University of Zielona Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland

autor

Adamski M.

• Computer Engineering & Electronics Department, University of Zielona Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland

Bibliografia

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• [3] D. Andreu, G. Souquet, and T. Gil, “Petri net based rapid prototyping of digital complex system,” in Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI. Washington, DC, USA: IEEE Computer Society, 2008, pp. 405–410, DOI: 10.1109/ISVLSI.2008.54.
• [4] G. Bazydło, “Graphical specification of programs for reconfigurable logic controllers using uml,” Ph.D. dissertation, University of Zielona Góra, 2010.
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• [6] M. Doligalski and M. Adamski, “Exceptions and deep history state handling using dual specification,” Electrical Review, vol. 9, no. 9, pp. 123–125, 2010.
• [7] G. Łabiak and M. Adamski, “Concurrent processes synchronisation in statecharts for fpga implementation,” in Design Test Symposium (EWDTS), 2008 East-West, oct. 2008, pp. 59–64, DOI: 10.1109/EWDTS.2008.5580158.
• [8] M. Doligalski and M. Wgrzyn, “Partial reconfiguration-oriented design of logic controllers,” Proceedings of SPIE : Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2007, vol. 6937, p. [10], 2007, DOI: 10.1117/12.784663.