Synthesis of FSMs Based on Architectural Decomposition with Joined Multiple Encoding

• Autorzy: Bukowiec A.
• Konferencja: International Conference on System Engineering - ICSEng (21 ; 16-18.08.2011) ; Las Vegas, USA
• Języki publikacji: EN

Abstrakty

EN

The method of synthesis of the logic circuit of finite state machine (FSM) with Mealy's outputs is proposed in this paper. Proposed method is based on the innovate encoding of microinstructions split into subsets. Code of microinstruction is represented as a part of current state code and code of microinstruction inside of current subset. It leads to realization of FSM as s double-level structure. It leads to diminishing of number of variables required for encoding of microinstructions. Such approach permits to decrease the number of required outputs of combinational part of FSM.

Słowa kluczowe

EN

Boolean algebra; circuit synthesis; field programmable gate array; FPGA; sequential circuits

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2012
• Tom: Vol, 58, No. 1
• Strony: 35--41
• Opis fizyczny: Bibliogr. 19 poz., tab.

Twórcy

autor

Bukowiec A.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

Bibliografia

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