UML Modelling in Rigorous Design Methodology for Discrete Controllers

• Autorzy: Łabiak G. , Adamski M. , Doligalski M. , Tkacz J. , Bukowiec A.
• Konferencja: International Conference on System Engineering - ICSEng (21 ; 16-18.08.2011) ; Las Vegas, USA
• Języki publikacji: EN

Abstrakty

EN

The paper presents an application of UML technology in a discrete system development process. In the process at the analysis stage UML diagrams are fundamental tool. The outcome of this stage is a basis for formal models exploited at the design stage, where the design is symbolically verified and treated as a rule-based system. Two formal models of good graphical appeal are proposed: Petri nets and state machine diagrams. Both are heavily using Boolean expressions what makes that design can easily be implemented in modern programmable structures.

Słowa kluczowe

EN

UML modelling; binary controller; decomposition; digital synthesis; formal analysis; verification

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2012
• Tom: Vol, 58, No. 1
• Strony: 27--34
• Opis fizyczny: Bibliogr. 18 poz., wykr.

Twórcy

autor

Łabiak G.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

autor

Adamski M.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

autor

Doligalski M.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

autor

Tkacz J.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

autor

Bukowiec A.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

• Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

Bibliografia

• [1] M. Adamski, M. Węgrzyn, and A. Karatkevich, Design of embedded control systems. New York: Springer, 2005.
• [2] G. Łabiak and G. Borowik, “Statechart-based controllers synthesis in fpga structures with embedded array blocks,” International Journal of Electronics and Telecommunications, vol. Vol. 56, no. no 1, pp. 13–24, 2010.
• [3] M. Doligalski and M. Węgrzyn, “Partial reconfiguration-oriented design of logic controllers,” Proceedings of SPIE : Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2007, vol. Vol. 6937, p. [10], 2007.
• [4] G. Booch, J. Rumbaugh, and I. Jacobson, The Unified Modeling Language. User Guide. New York: Addison Wesley Longman, Inc., 1999.
• [5] E. M. Clarke, O. Grumberg, and D. A. Peled, Model Checking. Cambridge, Massachusetts: The MIT Press, 1999.
• [6] P. Misurewicz, “Lectures on real-time microprocessor control systems,” in Lecture Notes. Twin Cities: University of Minnesota, 1976.
• [7] L. Gniewek and J. Kluska, “Hardware implementation of fuzzy Petri net as a controller,” IEEE Transactions on Systems, Man, and Cybernetics - Part B: Cybernetics, vol. Vol. 34, no. No. 3, pp. 1315–1324, 2004.
• [8] M. Doligalski and M. Adamski, “Exceptions and deep history state handling using dual specification,” Electrical Review, no. No. 9, pp. 123–125, 2010.
• [9] G. Čabiak and M. Adamski, “Concurrent processes synchronisation in statecharts for FPGA implementation,” in Proceedings of IEEE East-West Design & Test Symposium EWDTS’08, Kharkov National University of Radioelectronics. Lviv, Ukraine: Lviv, The Institute of Electrical and Electronics Engineers, Inc., 2008, pp. 59–64.
• [10] K. Biliński, M. Adamski, J. Saul, and E. Dagless, “Petri-net-based algorithms for parallel-controller synthesis,” IEE Proceedings - Computers and Digital Techniques, vol. Vol. 141, no. No. 6, pp. 405–412, 1994.
• [11] A. Karatkevich, Dynamic Analysis of Petri Net-Based Discrete Systems, ser. Lecture Notes in Control and Information Sciences. Berlin: Springer-Verlag, 2007, vol. 356.
• [12] A. Bukowiec and L. Gomes, “Partitioning of Mealy finite state machines,” in Preprints of the 4th IFAC Workshop Discrete-Event System Design DESDes’09, Gandia Beach, Spain, 2009, pp. 21–26.
• [13] A. Węgrzyn, “Parallel algorithm for computation of deadlocks and traps in Petri nets,” in 10th IEEE International Conference Emering Technologies and Factory Automation ETFA’05, vol. 1, Universita di Catania. Catania, Italy: Piscataway, IEEE Operation Center, 2005, pp. 143–148.
• [14] J. H. Gallier, Logic for Computer Science: Foundations of Automatic Theorem Proving. New York: Harper & Row Publishers, 1985. [Online]. Available: http://www.cis.upenn.edu/jean/gbooks/logic.html
• [15] J. Tkacz, “State machine type colouring of Petri net by means of using a symbolic deduction method,” Measurement Automation and Monitoring, vol. Vol. 53, no. No. 5, pp. 120–122, 2007.
• [16] M. Adamski, “Petri nets in ASIC design,” Applied Mathematics and Computer Science, vol. Vol. 3, no. No. 1, pp. 169–179, 1993.
• [17] M. Zwoliński, Digital System Design with VHDL, 2nd ed. New Jersy: Prentice Hall, 2004.
• [18] M. Puczyńska, G. Łabiak, and P. Wolański, “Programowa implementacja konwersji sieci petriego na język VHDL,” in Materiały III Krajowej Konferencji Naukowej Reprogramowalne Układy Cyfrowe RUC 2000, Szczecin, Poland, 2000, pp. 285–291.