Methodology for Implementing Scalable Run-Time Reconfigurable Devices

• Autorzy: Kotynia Ł. , Amrozik P. , Napieralski A.
• Języki publikacji: EN

Abstrakty

EN

The aim of this paper is to present the implementation methodology for an ASIC constituting the fine-grained array of dynamically reconfigurable processing elements. This methodology was developed during the work on a device which can operate as a typical Field Programmable Gate Array (FPGA) with some bio-inspired features or as a multi-core Single Instruction Multiple Data (SIMD) processor. Such high diversity of possible operating modes makes the design implementation extremely demanding. As a consequence, the comprehensive study and analysis of the different possible implementation techniques in this case allowed us to formulate a consistent and complete methodology that can be applied to other systems of similar structure.

Słowa kluczowe

EN

design reuse; floorplanning; FPGA; implementation; verification; reconfigurable logic; timing analysis

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2011
• Tom: Vol. 57, No. 2
• Strony: 177--183
• Opis fizyczny: Bibliogr. 15 poz., wykr.

Twórcy

autor

Kotynia Ł.

autor

Amrozik P.

autor

Napieralski A.

• Department of Microelectronics and Computer Science of Technical University of Lodz, Poland,

Bibliografia

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