Identyfikatory
Warianty tytułu
Języki publikacji
Abstrakty
The paper overviews optimization based statistical design centering techniques for analog circuits. Emphasis is placed on dependence between formulation of quality indices, problem formulation, and computational complexity of design centering algorithms, executed in single- or multiple-processor environments. For characterization of solution techniques a standard CMOS op-amp design case and a simplified computational complexity analysis are used.
Rocznik
Tom
Strony
159--167
Opis fizyczny
Bibliogr. 30 poz., wykr.
Twórcy
autor
- Institute of Electronic Systems, Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warsaw, Poland, L.Opalski@elka.pw.edu.pl
Bibliografia
- [1] J. Chen and M. Styblinski, “A systematic approach to statistical modeling and its application to CMOS circuits,” in Proc. ISCAS, 1993, pp. 1805–1808.
- [2] C. Michael and M. Ismail, Statistical modeling for computer-aided design of MOS VLSI circuits. Kluwer Acad. Publ., 1993.
- [3] M. Conti, P. Crippa, S. Orcioni, and C. Turchetti, “Parametric yield formulation of MOS IC’s affected by mismatch effect,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 5, pp. 582–596, May 1999.
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- [6] M. Stybliński and L. Opalski, “Algorithms and software tools for IC yield optimization based on fundamental fabrication parameters,” IEEE Trans. Comput.-Aided Design, vol. 5, no. 1, pp. 79–89, January 1986.
- [7] M. Pehl and H. Graeb, “RaGAzi: A random and gradient-based approach to analog sizing for mixed discrete and continuous parameters,” in Proc. ISIC, 2009, pp. 113–116.
- [8] W. Nye, D. Riley, and A. Sangiovanni-Vincentelli, “DELIGHT.SPICE: an optimization-based system for the design of integrated circuits,” IEEE Trans. Comput.-Aided Design, vol. 7, no. 4, pp. 501–519, April 1988.
- [9] M. Stybliński, “Design for circuit quality: yield maximization, minimax and Taguchi approach,” in Proc. ICCAD, 1990, pp. 112–115.
- [10] A. Müller, “Stochastic ordering of multivariate normal distributions,”Ann. Inst. Statist. Math., vol. 53, no. 3, pp. 567–575, 2001.
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- [12] R. Rutebnbar, G. Gielen, and J. Roychowdhury, “Hierarchical modeling, optimization and synthesis for system-level analog and RF designs,”Proc. of the IEEE, vol. 95, no. 3, pp. 640–669, March 2007.
- [13] J. Zhang and M. Styblinski, Yield and variability optimization of integrated circuits. Kluwer Acad. Publ., 1995.
- [14] R. Spence and R. Soin, Tolerance design of electronic circuits. Addison-Wesley, 1988.
- [15] L. Opalski, “Deterministic optimization of stochastic circuit quality measures,” in Proc. Nat’l Conf. on Ckt. Th. and El. Ckts. (in Polish), Polanica Zdrój, 1994, pp. 579–584.
- [16] M. Stybliński and A. Ruszczyński, “Stochastic approximation approach to production yield optimization,” Electronic Letters, vol. 19, no. 8, pp. 300–301, 1986.
- [17] B. Batalov, Y. Belyakov, and F. Kurmaev, “Some methods for statistical optimization of integrated microcircuits,” Soviet Microelectronics (USA), vol. 7, no. 4, pp. 228–238, July-August 1978.
- [18] J. Lonc and L. Opalski, “Yield optimization by stochastic programming with adaptive yield gradient estimator,” in Proc. Nat’l Conf. on Ckt. Th. and El. Ckts. (in Polish), Sulejów, Poland, 1982, pp. 141–156.
- [19] L. Opalski and M. Stybliński, “Generalization of yield optimization problem: maximum income approach,” IEEE Trans. Comput.-Aided Design, vol. 5, no. 2, pp. 346–360, April 1986.
- [20] R. Rubinstein, Simulation and the Monte Carlo Method. N. York: J. Wiley & Sons, 1981.
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- [22] J. Ogrodzki, “One-dimensional orthogonal search – a method for a segment approximation to acceptability region,” Circ. Th. and Applications, vol. 14, pp. 181–194, 1986.
- [23] A. Dharchoudhury and S. Kang, “Worst-case analysis and optimization of VLSI circuit performances,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 14, no. 4, pp. 481–492, April 1995.
- [24] L. Opalski, “Yet another approach to statistical circuit design – stochastic minimax,” in Proc. ISCAS, N. Orleans, LA, USA, 1990, pp. 2264–2267.
- [25] L. Opalski and M. Styblinski, “GOSSIP – a generic system for statistical circuit design,” in Proc. Euro-DAC, Hamburg, Germany, 1992, pp. 572–577.
- [26] G. Müller-L., “Limit parameters: the general solution of the worst-case problem for the linearized case,” in Proc. ISCAS, N. Orleans, LA, USA, 1990, pp. 2256–2269.
- [27] K. Antreich, H. Graeb, and C. Wieser, “Circuit analysis and optimization driven by worst-case distances,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 13, no. 1, pp. 57–71, January 1994.
- [28] A. Seifi, K. Ponnambalan, and J. Vlach, “A unified approach to statistical design centering of integrated circuits with correlated parameters,” IEEE Trans. Circuits Syst. I, vol. 46, no. 1, pp. 190–196, January 1999.
- [29] H. Graeb, Analog Design Centering and Sizing. Springer, 2007.
- [30] R. Schwencker, F. Schenkel, M. Pronath, and H. Graeb, “Analog circuit sizing using adaptive worst-case parameter sets,” in Proc. DATE Conf. and Exhib., 2002, pp. 581 – 585.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BWA0-0049-0029