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Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS Inverters

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The paper presents quarter-square analog four-quadrant multipliers, based on proprietary architecture using four CMOS inverters. The most important upgrade on already published own circuit implementation is the use of the same inverter "core" of the circuit with completely redesigned auxiliary and steering blocks. Two variants of new driving peripherals are considered: one with differential pair, the second with CMOS inverters. The proposed circuit solutions are suitable for RF applications in communication systems due to simple architecture comprising building blocks with RF CMOS transistors having sufficiently large biasing currents. Postlayout simulation results done on the basis of 180nm CMOS UMC Foundry Design Kit are also presented.
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  • Department of Electonics, AGH University of Technology, Mickiewicza 30, 30-059 Kraków, Poland, machowsk@agh.edu.pl
Bibliografia
  • [1] G. Han and E. Sanchez-Sinencio, “CMOS transconductance multipliers: a tutorial,” IEEE Trans. Circuits Syst. II, vol. 45, no. 12, pp. 1550-1563, Dec. 1998.
  • [2] M. Dei, N. Nizza, P. Bruschi, and M. Piotto, “A four quadrant CMOS analog multiplier based on the non ideal MOSFET I-V characteristics,” in Proceedings 2008 PhD Research in Microelectronics and Electronics, Apr. 2008, pp. 33-36.
  • [3] R. Hidayat, K. Dejhan, P. Moungnoul, and Y. Miyanaga, “Ota-based high frequency CMOS multiplier and squaring circuit,” in Intelligent Signal Processing and Communications Systems. International Symposium on, Feb. 2009, pp. 1-4.
  • [4] C. Chen and Z. Li, “A low-power CMOS analog multiplier,” Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 53, no. 2, pp. 100-104, Feb. 2006.
  • [5] C. J. Debono, F. Maloberti, and J. Micallef, “A low-voltage CMOS multiplier for RF applications,” in ISLPED ’00: Proceedings of the 2000 international symposium on Low power electronics and design. New York, NY, USA: ACM, 2000, pp. 225-227.
  • [6] B. Gilbert, “A precise four-quadrant multiplier with subnanosecond response,” Solid-State Circuits, IEEE Journal of, vol. 3, no. 4, pp. 365-373, Dec. 1968.
  • [7] H.-J. Song and C.-K. Kim, “An mos four-quadrant analog multiplier using simple two-input squaring circuits with source followers,” Solid-State Circuits, IEEE Journal of, vol. 25, no. 3, pp. 841-848, Jun. 1990.
  • [8] J. Crols and M. Steyaert, “A 1.5 GHz highly linear CMOS downconversion mixer,” Solid-State Circuits, IEEE Journal of, vol. 30, no. 7, pp. 736-742, Jul. 1995.
  • [9] S.-Y. Hsiao and C.-Y. Wu, “A parallel structure for CMOS four-quadrant analog multipliers and its application to a 2-GHz rf downconversion mixer,” Solid-State Circuits, IEEE Journal of, vol. 33, no. 6, pp. 859-869, Jun. 1998.
  • [10] A. Shahani, D. Shaeffer, and T. Lee, “A 12-mw wide dynamic range CMOS front-end for a portable gps receiver,” Solid-State Circuits, IEEE Journal of, vol. 32, no. 12, pp. 2061-2070, Dec. 1997.
  • [11] H. Barthelemy, M. Fillaud, S. Bourdel, and J. Gaubert, “CMOS inverters based positive type second generation current conveyor,” Analog Integrated Circuits and Signal Processing, vol. 50, pp. 141-146, 2007.
  • [12] M. Elnozahi and Y. Massoud, “Efficient synthesis methodology for optimal inverter-based transimpedance amplifiers,” Analog Integrated Circuits and Signal Processing, vol. 50, pp. 205-211, 2007.
  • [13] W. Machowski, “CMOS inverter based analog multipliers,” Przegld Elektrotechniczny, vol. 86, no. 4, pp. 209–212, 2010.
  • [14] W. Machowski, S. Kuta, and J. Jasielski, “Four-quadrant analog multiplier based on CMOS inverters,” Analog Integr. Circuits Signal Process., vol. 55, no. 3, pp. 249-259, 2008.
  • [15] B. Nauta and E. Seevinck, “Linear CMOS transconductance element for vhf filters,” Electronics Letters, vol. 25, no. 7, pp. 448-450, Mar. 1989.
  • [16] W. Machowski, S. Kuta, J. Jasielski, and W. Kołodziejski, “Quartersquare analog four-quadrant multiplier based on CMOS invertes and using low voltage high speed control circuits,” in Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems, Jun. 2010, pp. 333–336.
  • [17] W. Machowski, S. Kuta, J. Jasielski, and W. Kołodziejski,“Broadband quarter-square 4Q analog multiplier based on CMOS inverters,” in International Conference on Signals and Electronic Systems, Sep. 2010, pp. 237-240.
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bwmeta1.element.baztech-article-BWA0-0046-0024
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