Architecture Design of The Hardware H.264/AVC Video Decoder

• Autorzy: Roszkowski M. , Abramowski A. , Wieczorek M. , Pastuszak G.
• Języki publikacji: EN

Abstrakty

EN

The need for real-time video compression systems requires a particular design methodology to achieve high troughput devices. The paper describes the architecture of the H.264/AVC decoder able to support SDTV and HDTV resolutions. The design applies many optimization techniques to reduce the resource consumption and maximize the throughput. The archietcture is verified with the software reference model JM16 and synhesized for FPGA technology. The maximal working frequency is 100 MHz for Stratix II devices.

Słowa kluczowe

EN

H.264/AVC; video compression; FPGA; architecture design

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2010
• Tom: Vol. 56, No. 3
• Strony: 291--300
• Opis fizyczny: Bibliogr. 12 poz., wykr.

Twórcy

autor

Roszkowski M.

autor

Abramowski A.

autor

Wieczorek M.

autor

Pastuszak G.

• Institute of Radioelectronics, Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warsaw, Poland,

Bibliografia

• [1] T.-W. Chen, Y.-W. Huang, T.-C. Chen, Y.-H. Chen, C.-Y. Tsai, and L.-G. Chen, “Architecture design of h.264/avc decoder with hybrid task pipelining for high definition videos,” in IEEE International Symposium on Circuits and Systems 2005, 23-26 2005, pp. 2931-2934 Vol. 3.
• [2] T.-C. Chen, H.-C. Fang, C.-J. Lian, C.-H. Tsai, Y.-W. Huang, T.-W. Chen, C.-Y. Chen, Y.-H. Chen, C.-Y. Tsai, and L.-G. Chen, “Algorithm analysis and architecture design for hdtv applications - a look at the h.264/avc video compressor system,” IEEE Circuits and Devices Magazine, vol. 22, pp. 22-31, May-June 2006.
• [3] H. Eeckhaut, M. Christiaens, D. Stroobandt, and V. Nollet, “Optimizing the critical loop in the h.264/avc cabac decoder,” in IEEE International Conference on Field Programmable Technology, 2006., dec. 2006, pp. 113-118.
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• [5] Y.-W. Huang, B.-Y. Hsieh, T.-C. Chen, and L.-G. Chen, “Analysis, Fast Algorithm, and VLSI Architecture Design for h.264/avc Intra Frame Coder,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, pp. 378-401, May 2005.
• [6] Recommendation ITU-T H.264(2007) - Corrigendum 1, Joint Video Team of ITU-T VCEG and ISO/IEC MPEG, January 2009.
• [7] Report of The Formal Verification Tests on AVC (ISO/IEC 14496-10 - ITU-T Rec. H.264), JVT, Test and Video Group, December 2003,Waikoloa.
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• [9] D. Marpe, T. Wiegand, and S. Gordon, “H.264/MPEG4-AVC Fidelity Range Extensions:Tools, Profiles, Performance, and Application Areas,” in IEEE International Conference on Image Processing 2005., vol. 1, September 2005, pp. 593-596.
• [10] I. E. G. Richardson, H.264 and MPEG-4 Video Compression. John Wiley & Sons, 2003.
• [11] W. T. Staehler, E. A. Berriel, A. A. Susin, and S. Bampi, “Architecture of an hdtv Intraframe Predictor for a h.264 Decoder,” in IFIP International Conference on Very Large Scale Integration, October 2006, pp. 228-233.
• [12] C.-H. Tsai, Y.-W. Huang, and L.-G. Chen, “Algorithm and architecture optimization for full-mode encoding of h.264/avc intra prediction,” in 48th Midwest Symposium on Circuits and Systems, 2005., vol. 1, August 2005, pp. 47-50.