Identyfikatory
Warianty tytułu
Języki publikacji
Abstrakty
The following paper describes an application of reconfigurable hardware architectures for processing of huge data streams. Radar, sonar and high speed internet networks are typical sources of data that require extreme computing power and resources to enable real time acquisition, processing and management. An approach to monitoring of real time multi-gigabit internet network has been described as a practical application of FPGA based board, designed for fast data processing.
Rocznik
Tom
Strony
107--110
Opis fizyczny
Bibliogr. 5 poz.
Twórcy
autor
autor
- Microtech International S.A., Wołoska 20, 51-116 Wrocław, Poland, a.handzlik@microtech.com.pl
Bibliografia
- [1] Z. Bankovic, D. Stepanovic, S. Bojanic, and O. Nieto-Taladriz, Efficient application of genetic algorithm and a dimension reduction technique for intrusion detection”, in Proc. 2006 International Conference on Engineering and Mathematics (E"MA 2006), 2006, pp. 303-308.
- [2] D. Barbara, N. Wu, and S. Jajodia, “Detecting novel network intrusions using Bayes estimators”, In Proc. the First SIAM Int. Conf. on Data Mining (SDM 2001), Chicago. Society for Industrial and Applied Mathematics (SIAM), 2001.
- [3] W. Lu and I. Traore, “Detecting new forms of network intrusion using genetic programming, Computational Intelligence, vol. 20, No. 3, 2004.
- [4] G. Shafer, A Mathematical Theory of Evidence, Princeton University Press, Princeton, 1976.
- [5] A. Skotarczyk and A. Chorazyczewski, “FastMatch System – semantic integration of threat detection methods in networks at high transmission
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BWA0-0045-0017