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Warianty tytułu
Konferencja
Digital Control Units Design ; 6.03.2009 ; Zielona Góra, Poland
Języki publikacji
Abstrakty
A method of combined state assignment is proposed which targets on a decrease in the hardware amount (the number of PAL macrocells) in combinational part of Moore nnite-state-machine (FSM). Some peculiarities of Moore FSM such as existence of pseu-doequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount. It allows hardware amount decrease without decreasing in performance of the controlled digital system. An example of application of proposed method is given. Some results of experiments based on the probabilistic approach are demonstrated. It is shown that the proposed method always leads to decrease in the hardware amount in comparison with the known methods of Moore FSM synthesis.
Czasopismo
Rocznik
Tom
Strony
317--333
Opis fizyczny
Bibliogr. 19 poz., wykr.
Twórcy
autor
autor
autor
- University of Zielona Góra, Institute of Electrical Engineering, ul prof. Z. Szafrana 2, 65-516 Zielona Góra, A.Barkalov@ii.uz.zgora.pl ; L.Titarenko@iie.uz.zgora.pl ; S.Chmielewski@weit.uz.zgora.pl
Bibliografia
- 1. S. Baranov: Logic and System Design of Digital Systems. Tallinn: TUT Press, 2008.
- 2. A. Barkalov and M. Węgrzyn: Design of Control Units with Programmable Logic. Zielona Góra: University of Zielona Góra Press, 2006.
- 3. C. Maxfield: The Design Warrior's Guide to FPGAs. Amsterdam: Elsevier, 2004.
- 4. Z. Navabi: Embedded Core Design with FPGAs. N.Y.: McGraw Hill, 2007.
- 5. http://www.altera.com
- 6. http://www.xilinx.com
- 7. D. Kania: Logic Synthesis Oriented on Programmable Logic Devices of the PAL type. Gliwice: Silesian Technical University, 2004, (in Polish).
- 8. G. De Micheli: Synthesis and Optimization of Digital Circuits. N.Y.: McGraw Hill, 1994.
- 9. S. Devadas, H.-K. Ma, R. Newton, A. Sangiovanni-Vincentelli: State Assignment of Finite State Machines Targeting Multilevel Logic Implementations. IEEE Transactions on Computer-Aided Design, 1988, vol. 7, pp. 1290-1300.
- 10. T. Kam, T. Villa, R. Brayton, A. Sangiovanni-Vincentelli: Synthesis of Finite State Machines: Functional Optimization. Boston/London/Dordrecht: Kluwer Academic Publishers, 1998.
- 11. T. Villa, T. Kam, R. Brayton, A. Sangiovanni-Vincentelli: Synthesis of Finite State Machines: Logic Optimization. Boston/London/Dordrecht: Kluwer Academic Publishers, 1998.
- 12. S. Chattopadhyay: Area Conscious State Assignment with Flip-Flop and Output Polarny Selection for Finite State Machine Synthesis: A Genetic Algorithm Approach. The Computer Journal,2005, vol. 48, no 4, pp. 443-450.
- 13. Y. Xiaand A. Almaini: Genetic algorithm based state assignment for power and area optimization. IEEP. - Comput. Dig. T., 2002, vol. 149, pp. 128-133.
- 14. A. Barkalov: Principles of Optimization of logical circuit of Moore FSM. Cybernetics and system analysis. 1998, no 1, pp. 65-72 (in Russian).
- 15. V. Solovjev: Design of Digital Systems Using the Programmable Logic Integrated Circuits. Moscow: Hotline - Telecom, 2001, (in Russian).
- 16. A. Barkalov, L. Titarenko, S. Chmielewski: Reduction in the number of PAL macrocells in the circuit of a Moore FSM. International Journal of Applied Mathematics and Computer Science, 2007, vol. 17, no 4, pp. 565-675.
- 17. A. Barkalov, L. Titarenko, S. Chmielewski: Optimization of Moore FSM on System-on-Chip. IEEE East-West Design & Test Symposium, Kharkov, 2007, pp. 105-109.
- 18. A. Barkalov: Design of Mealy finite-state-machines with the transformation of objects codes. International Journal of Applied Mathematics and Computer Science, 2005, vol. 15, no 1, pp. 151-158.
- 19. S. Yang: Logic Synthesis and Optimization Benchmarks User Guide. Microelectronics Center of North Carolina, Research Triangle Park, North Carolina, 1991.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BWA0-0041-0009