Hardware reduction for Moore FSM implemented with CPLD

• Autorzy: Barkalov A. , Titarenko L. , Chmielewski S.
• Konferencja: Digital Control Units Design ; 6.03.2009 ; Zielona Góra, Poland
• Języki publikacji: EN

Abstrakty

EN

A method of combined state assignment is proposed which targets on a decrease in the hardware amount (the number of PAL macrocells) in combinational part of Moore nnite-state-machine (FSM). Some peculiarities of Moore FSM such as existence of pseu-doequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount. It allows hardware amount decrease without decreasing in performance of the controlled digital system. An example of application of proposed method is given. Some results of experiments based on the probabilistic approach are demonstrated. It is shown that the proposed method always leads to decrease in the hardware amount in comparison with the known methods of Moore FSM synthesis.

Słowa kluczowe

EN

Moore finite-state-machine; synthesis; graph-scheme of algorithm; CPLD; PAL; macrocell; pseudoequivalent states

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: Electronics and Telecommunications Quarterly
• Rocznik: 2009
• Tom: Vol. 55, No 2
• Strony: 317--333
• Opis fizyczny: Bibliogr. 19 poz., wykr.

Twórcy

autor

Barkalov A.

autor

Titarenko L.

autor

Chmielewski S.

• University of Zielona Góra, Institute of Electrical Engineering, ul prof. Z. Szafrana 2, 65-516 Zielona Góra,

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