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Structural decomposition of finite state machines

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Digital Control Units Design ; 6.03.2009 ; Zielona Góra, Poland
Języki publikacji
EN
Abstrakty
EN
New architectures of FPGA devices combine different type of logic elements like look-up tables, flip-flops and memory blocks. But standard synthesis methods utilize only look-up tables and flip-flops and it makes that device utilization is not optimal one. Methods of synthesis and implementation of Mealy finite state machines into FPGAs there are presented in this article. Synthesis methods are based on the architectural decomposition of logic circuit of FSM and multiple encoding of some its parameters. Architectures of such designed structures are based on existence of decoders as second-level circuits. There is also proposed hardware implementation into FPGAs of developed multi-level structures. The hardware implementation is based on an implementation with use of look-up tables and memory blocks together. The combinational circuit and the register are implemented with use of logic blocks, like in standard realizations. While, decoders are implemented with use of memory blocks. Such realization leads to balanced and rational usage of hardware resources of modern FPGA devices.
Słowa kluczowe
Rocznik
Strony
243--267
Opis fizyczny
Bibliogr. 32 poz., wykr.
Twórcy
autor
autor
Bibliografia
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  • 8. A. Barkalov, A. Bukowiec, (2004): Synthesis of control unit with multiple encoding of the sets of microoperations. In: Proceedings of the 2nd International Workshop on Discrete-Event System Design DESDes'04, pp. 75-78, Dychów, Poland: University of Zielona Góra Press.
  • 9. A. Barkalov, A. Bukowiec, (2004): Synthesis of Mealy FSM with transformation of system of microoperations in excitation functions. Radioelectronics and Computer Science, No. 3, 82-85.
  • 10. A. Barkalov, A. Bukowiec, (2005): Optimization of Mealy FSM with decoding of the microoperations system. Control Systems and Computers, No 5, 51-56.
  • 11. A. Barkalov, A. Bukowiec, (2007): Realization of Mealy automata with transformation of microoperations in the registers excitation functions. In: Proceedings of the 6th International Conference on Computer-Aided Design of Discrete Devices CAD DD'07 vol. 2, pp. 34-38, Minsk, Belarus.
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  • 14. A. Bukowiec, (2004): Synthesis of Mealy automata with multiple encoding of internal states. In: Proceedings of Scientific Conference Computer Science - Art or Craft KNWS'04, pp. 29-34, Zamek Czocha, Poland: University of Zielona Góra Press.
  • 15. A. Bukowiec, (2005): Automata synthesis with application of multiple encoding. In: Proceedings of 2nd Scientific Conference Computer Science - Art or Craft KNWS'05, pp. 17-22, Złotniki Lubańskie, Poland: University of Zielona Góra Press.
  • 16. A. Bukowiec, (2006): Synthesis of Mealy FSM with multiple shared encoding of microinstructions and internal states. In: Proceedings of IFAC Workshop on Programmable Devices and Embedded Systems PDeS'06, pp. 95-100, Brno, Czech Republic.
  • 17. A. Bukowiec, (2008): Synthesis of Finite State Machines for Programmable Devices Based on Multi-Level Implementation. Ph. D. Thesis, University of Zielona Góra. Faculty of Electrical Engineering, Computer Science and Telecommunications. Supervisor Prof. A. Barkalov, Ph.D. D.Sc.
  • 18. A. Bukowiec, (2008): Automata Synthesis System, available at http://willow.iie.uz.zgora.pl/~abukowie/AS/as.htm
  • 19. A. Bukowiec, A. Barkalov, L. Titarenko, (2008): FSMs implementation into FPGAs with multiple encoding of states. In: Proceedings of IEEE East-West Design & Test Symposium EWDTS'08, pp. 72-75, Lviv, Ukraine: ŒEE.
  • 20. K. Figler, (2006): Analysis of Formal Methods of Synthesis of One-Level Finite State Machines. Master's thesis. University of Zielona Góra, Faculty of Electrical Engineering, Computer Science and Telecommunications. Supervisor: Prof. A. Barkalov, Ph.D. D.Sc, co-supervisor: A. Bukowiec, M.Sc. (in Polish).
  • 21. A. Jantsch, (2003): Modeling Embedded Systems and SoC's: Concurrency and Time in Models of Computation. San Francisco: Morgan Kaufmann.
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  • 27. M. Rawski, P. Morawiecki, H. Selvaraj, (2006): Decomposition of combinational circuits described by large truth tables. In: Proceedings of the 8th International Conference on Systems Engineering ICSE'06, pp. 401-406, Coventry, United Kingdom.
  • 28. Z. Salcie, (1998): VHDL and FPLDs in Digital Systems Design, Prototyping and Customization. Boston: Kluwer Academic Publishers.
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Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BWA0-0041-0006
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