Structural decomposition of microprogrammed controllers

Wiśniewski, R.; Barkalov, A.

Artykuł - szczegóły

Tytuł artykułu

Structural decomposition of microprogrammed controllers

Autorzy

Wiśniewski R. , Barkalov A.

Wybrane pełne teksty z tego czasopisma

http://ijet.pl/index.php/ijet

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Warianty tytułu

Konferencja

Digital Control Units Design ; 6.03.2009 ; Zielona Góra, Poland

Języki publikacji

Abstrakty

The paper focuses on the structural decomposition of control units. Eight methods of compositional microprogram control units are described and compared. Proposed solutions can be divided into two main groups. The first one deals with CMCUs with mutual memory, where the internal code of the controller is recognized by the microinstruction address. The second group of presented methods is based on control units with sharing codes, where the microinstruction address is formed as a concatenation of codes generated by the counter and by the register. The aim of all proposed solutions is to reduce the number of logic blocks of the destination programmable device.

Słowa kluczowe

control units microprogrammed controllers compositional microprogram control unit CMCU programmable devices field programmable gate array FPGA

Wydawca

Polish Academy of Sciences, Committee of Electronics and Telecommunication

Czasopismo

Electronics and Telecommunications Quarterly

Rocznik

2009

Tom

Vol. 55, No 2

Strony

215--241

Opis fizyczny

Bibliogr. 94 poz., wykr.

Twórcy

autor

Wiśniewski R.

autor

Barkalov A.

University of Zielona Góra, ul. Podgórna 50, 65-246 Zielona Góra, Poland, Wisniewski@iie.uz.zgora.pl ; A.Barkalov@iie.uz.zgora.pl

Bibliografia

1. G. De Micheli: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York, 1994.
2. A. Clements: The principles of computer hardware. Oxford University Press, New Jersey, 2000.
3. T. Łuba: Synteza układów cyfrowych. WKŁ Warszawa, 2003.
4. M. Bolton: Digital Systems Design with Programmable Logic. Addison-Wesley Longman Publishing Co., Inc., Boston, MA, USA, 1990.
5. D. Bursky: Embedded logic and memory find a home in FPGAs. Electronic Design, 1999, vol. 47, no 14, pp. 43-56.
6. D. Gajski: Principles of Digital Design. Prentice Hall, New Jersy, 1997.
7. G. Mealy: A method for synthesizing sequential circuits. BSTJ, 1955, vol. 34, pp. 1045-1079.
8. E. Moore: Gedanken experiments on sequential machines. In C. E. Shannon and J. McCarthy, editors, Automata Studies, 1956, pp. 129-153.
9. Altera: Embedded memory in Altera FPGAs. Altera, http://www.altera.com/technology/memory/embedded/mem-embedded.html, 2006.
10. Xilinx: Using Block SelectRAM+ Memory in Spartan-II FPGAs. www.xilinx.com/bvdocs/appnotes/xappl30.pdf, 2000.
11. T. Łuba: Synteza układów logicznych. Oficyna Wydawnicza PW, Warszawa, 2005.
12. S. I. Baranov: Logic Synthesis for Control Automata. Kluwer Academic Publishers, Boston, 1994.
13. A. Barkalov: Synthesis of Control Units on PLDs. DonNTU, Donetsk, 2002.
14. R. Wiśniewski: Częściowa rekonfiguracja mikroprogramowanych układów sterujących implementowanych z wykorzystaniem struktur FPGA. Proceedings of PTETIS, 2005, Vol. 21, ss. 239-242.
15. Xilinx: Two flows for partial reconfiguration. http://direct.xilinx.com/bvdocs/appnotes/xapp290.pdf, 2004.
16. M. Węgrzyn: Design of Control Units with Programmable Logic. University of Zielona Góora Press, Zielona Góra, 2006.
17. T. Łuba: Synteza układów logicznych. WSISiZ, Warszawa, 2001.
18. M. Molski: Modułowe i mikroprogramowalne układy cyfrowe. WKŁ, Warszawa, 1986.
19. W. Traczyk: Układy cyfrowe. Podstawy teoretyczne i metody syntezy. WNT, Warszawa, 1982.
20. M. Adamski, M. Węgrzyn, A. Węgrzyn: Safe reconfigurable logic controllers design. In ed. by J. Korbicz, editor, Measurements models systems and design, WKŁ, 2007, pp. 343-370.
21. M. Adamski and M. Węgrzyn: Reprogrammable controllers for reactive embedded systems. Proceedings volume from the 26th IFAC/IFIP/IEEE Workshop, Elsevier, Oxford, 2003, pp. 39-44.
22. M. Adamski: Programowane asynchroniczne układy sterujące z samosynchronizacją. KKA'80, 1980, Szczecin, Polska, ss. 203-208.
23. E. Sentovich, K. J. Singh, Cho W. Moon, H. Savoj, R. K. Brayton, A. L. Sangiovanni-Vincentelli: Sequential circuit design using synthesis and optimization. Proceedings of the ICCD '92, 1992, Washington, DC, USA, pp. 328-333.
24. E. Hrynkiewicz, K. Pucher, D. Kania: The input partitioning and coding problem in PAL -based CPLD s. XX National Conference Circuit Theory and Electronic Networks, 1997, pp. 145-152.
25. P. Ashar, S. Devadas, A. R. Newton: A unified approach to the decomposition and re-decomposition of sequential machines. Proceedings of the 27th ACM/IEEE conference on DAC, New York, NY, USA, 1990, pp. 601-606.
26. P. Ashar, S. Devadas, A. R. Newton: Sequential Logic Synthesis. Kluwer Academic Publishers, Norwell, MA, USA, 1992.
27. H. Kubatova: Finite state machine implementation in FPGAs., Design of Embedded Control Systems, Springer, New York, 2005, pp. 177-187.
28. M. Perkowski, L. Jóźwiak, W. Zhao: Symbolic two-dimensional minimization of strongly unspecified finite state machines. Journal of Systems Architecture, Vol. 47, 2001, pp. 15-28.
29. M. Rawski, H. Selvaraj, T. Łuba: An application of functional decomposition in rom-based fsm implementation in FPGA devices. Proceedings of the DSD '03, Washington, DC, USA, 2003, p. 104.
30. A. Barkalov: Principles of optimization of logical circuit of Moore finite state-machine. Cybernetics and System Analysis, no. 1, 1998, pp. 65-72.
31. I. Ahmad, F. Ali, and R. Ul-Mustafa: An Integrated State Assignment and Flip-Flop for Selection Technique FSM Synthesis. Microprocessors and Microsystems, 2000, pp. 141-152.
32. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli: SIS: A system for sequential circuit synthesis. Technical Report UCB/ERL M92/41, U.C. Berkeley, 1992.
33. M. V. Wilkes: The best way to design an automatic calculating machine. Manchester University inaugural conference, Manchester, England, 1951.
34. S. S. Husson: Microprogramming - Principles and Practices. Prentice Hall, New York, 1970.
35. L. Kravcov, G. Chernicki: Design of microprogram control units. Energia, Leningrad, 1976 (in Russian).
36. P. Misiurewicz: Podstawy techniki cyfrowej. WNT, Warszawa, 1982.
37. Ch. A. Papachristou: A scheme for implementing microprogram addressing with programmable logic arrays. Digital Processes, vol. 5, no. 3-4, 1979, pp. 235-256.
38. W. Stalings: Computer organization and architecture. Prentice Hall, New Jersey, 1996.
39. A. Barkalov, A. Palagin: Synthesis of Microprogram Control Units. IC NAC of Ukraine, Kiev, 1997.
40. M. Adamski, A. Barkalov: Architectural and Sequential Synthesis of Digital Devices. University of Zielona Góra Press, Zielona Góra, 2006.
41. D. Kania, J. Kulisz, A. Milik, R. Czerwieński: Modele dekompozycji przeznaczone dla struktur matrycowych. RUC'2005, ss. 77-84, 2005.
42. S. Devadas, A. R. Wang, A. R. Newton, and A. L. Sangiovanni-Vincentelli: Boolean decomposition of programmable logic arrays. CICC'88, 1988.
43. T. Sasao: Totally undecomposable functions: Applications to efficient multiple-valued decompositions. ISMVL '99: Proceedings of the ISMVL '99, Washington, DC, USA, 1999, p. 59.
44. E. McCluskey: Logic design principles. Prentice Hall, Englewood, 1986.
45. M. Rawski, T. Łuba, Z. Jachna, P. Tomaszewicz: The influence of functional decomposition on modern digital design process. Design of Embedded Control Systems, Springer, Boston, 2005, pp. 193-206.
46. C. Scholl: Functional decomposition with application to FPGA synthesis. Kluwer Academic Publishers, 2001.
47. D. Kania, J. Kulisz: Logic synthesis for PAL-based CPLD-s based on two-stage decomposition. J. Syst. Softw., 80(7), 2007, pp. 1129-1141.
48. D. Kania: A new approach to logic synthesis of multi-output boolean functions on PAL -based CPLD s. Proceedings of the GLSVLSI '07, New York, NY, USA, 2007, pp. 152-155.
49. T. Łuba, M. Rawski, Z. Jachna: Functional decomposition as a universal method of logic synthesis for digital circuits. Proceedings of the MixDes'02, Wrocław, Poland, 2002, pp. 285-290.
50. M. Rawski, L. Jóźwiak, T. Łuba: Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures. Journal of Systems Architecture, vol. 47, 2001, pp. 137-155.
51. D. Kania: Synteza logiczna przeznaczona dla matrycowych struktur programowalnych typu PAL. Zeszyty Naukowe Politechniki Śląskiej, Gliwice, 2004.
52. D. Kania: Two-level logic synthesis on PAL-based CPLD and FPGA using decomposition. Procedings of 25-th Euromicro Conference. IEEE Computer Society Press, 1999, pp. 278-281.
53. M. Ciesielski, S. Yang: PLA de: a two-stage PLA decomposition. IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 11(8), 1992, pp. 943-954.
54. S. Devadas, A. Wang, R. Newton, and A. L. Sangiovanni-Vincentelli: Boolean decomposition in multilevel logic optimization. IEEE Journal of solid-state circuits, 1989, pp. 399-408.
55. V. Muthukumar, R. J. Bignall, H. Selvaraj: An efficient variable partitioning approach for functional decomposition of circuits. J. Syst. Archit., no. 53 (1), 2007, pp. 53-67.
56. E. M. Sentovich: Sequential Circuit Synthesis at the Gate Level. Ph D Thesis, 1993. (Chair-Robert K. Brayton).
57. V. Solovjev: Design of the Functional Units of Digital Systems Using Programmable Logic Devices. Bestprint, Minsk, 1996.
58. J. Lach, E. Sapiecha, B. Zbierzchowski: Synteza układów sekwencyjnych w strukturach FPGA z wbudowanymi blokami pamięci. Przegląd Telekomunikacyjny i Wiadomości Telekomunikacyjne, nr 2-3, 2003, ss. 81-86.
59. J. Pasierbiński, P. Zbysiński: Układy programowalne w praktyce. WKŁ, Warszawa, 2001.
60. Rawski, P. Tomaszewicz, H. Selvaraj, T. Łuba: Efficient implementation of digital filters with use of advanced synthesis methods targeted FPGA architectures. Proceedings of DSD '05, Washington, DC, USA, 2005, pp. 460-466.
61. H. Selvaraj, T. Łuba: A balanced multilevel decomposition method. Proceedings of EDTC '95, Washington, DC, USA, 1995, p. 594.
62. G. Borowik: Synteza układów sekwencyjnych w sieciach wbudowanych matryc logicznych struktur FPGA. Proceedings of OWD'04, vol. 19, Wisła, Polska, 2004, ss. 361-366.
63. G. Borowik: FSM coding for optimal serial decomposition. Proceedings of OWD'05, vol. 21, Wisla, Polska, 2005, pp. 243-248.
64. A. Barkalov, L. Titarenko, R. Wiśniewski: Synthesis of compositional microprogram control units with transformation of the numbers of inputs. Proceedings of CADSM 2005, Lviv - Polyana, Ukraina, 2005, pp. 181-184.
65. A. Barkalov, R. Wiśniewski: Design of compositional microprogram control units with maximal encoding of inputs. Radioelektronika i Informatika, no 3, 2004, pp. 79-81.
66. A. Barkalov, R. Wiśniewski: Design of compositional microprogram control units with transformation of the number of transactions. Proceedings of MIXDES'04, Szczecin, Polska, 2004, pp. 172-175.
67. A. Barkalov, R. Wiśniewski, R. Babakov: Optimizacija kompozicionnogo mikroprogramnogo ustrojstva upravlenija s elementarnymi operatornymi linejnymi celjami. Naukovi Praci DNTU: Obcisljuval'na Technika ta Avtomatizacija, nr 77, 2004, pp. 210-216 (in russian).
68. A. Barkalov, R. Wiśniewski: Optimization of compositional microprogram control unit with elementary operational linear chains. Upravljuscije Sistemy i Masiny, no. 5, 2004, pp. 25-29.
69. A. Barkalov, R. Wiśniewski: Synthesis of compositional microprogram control units with transformation of the numbers of inputs. Proceedings of DESDes' 04, Zielona Góra, 2004, pp. 145-148.
70. A. Barkalov, R. Wiśniewski: Design of control units with transformation of the number of transaction. Radiotechnika, Charkivskij nacionalnij universitet radioelektroniki, Charkiv, no 138, 2004, pp. 110-113.
71. A. Barkalov, A. Bukowiec, R. Wiśniewski: Sintez mikroprogrammnogo avtomata s predstavleniem termov funkcij vozbuzdenija kak par mikrokomand. Radiotechnika, Charkivs'kij nacional'nij universitet radioelektroniki, Charkiv, 2005, no 142, pp. 92-96.
72. R. Wiśniewski: Projektowanie układów mikroprogramowanych z wykorzystaniem wbudowanych bloków pamięci w matrycach programowalnych. Proceedings of KNWS' 05, Złotnik) Lubańskie, Polska, 2005, ss. 33-38.
73. Xilinx: Using Block RAM in Spartan-3 Generation FPGAs. www.xilinx.com/bvdocs/appnotes/xapp463.pdf, 2005.
74. Altera: Altera Devices Website. Http://www.altera.com/products/devices/dev-index.jsp, 2008.
75. A. Barkalov, M. Węgrzyn, R. Wiśniewski: Partial reconfiguration of compositional microprogram control units implemented on FPGAs. Proceedings of PDeS 2006, Brno, Czech Rep., 2006, pp. 116-119.
76. D. Mesquita, F. Moraes, J. Palma, L. Moller, N. Calazans: Remote and partial reconfiguration of FPGAs: Tools and trends. Proc. of IPDPS'03, 2003, pp. 177-185.
77. A. Barkalov, L. Titarenko, R. Wiśniewski: Optimization of the amount of LUT-elements in compositional microprogram control unit with mutual memory. Proc. of EWDTW '05, Odessa, Ukraine, 2005, pp. 75-79.
78. R. Wiśniewski, A. Barkalov: Synthesis of compositional microprogram control units with function decoder. Proc. of IWCIT 2007, Ostrava, Czech Rep., 2007, pp. 229-232.
79. A. Barkalov, M. Węgrzyn, R. Wiśniewski: Optimization of LUT-elements amount in cotrol unit of system-on-chip. Proceedings of DESDes '06, Rydzyna, Poland, 2006, pp. 143-146.
80. R. Wiśniewski, A. Barkalov, L. Titarenko: Synthesis of compositional microprogram control units with OLC output identification. Proceedings of CAD DD 2007, vol 2, Minsk, Belarus, 2007, pp. 81-86.
81. A. Barkalov, L. Titarenko, R. Wiśniewski: Synthesis of compositional microprogram control units with function decoder for telecommunication systems. Radiotehnika: Problemy telekommunikativ no 151, Charkivskij nacionalnij universitet radioelektroniki, Charkiv, 2007, pp. 106-111.
82. A. Barkalov, R. Wiśniewski: Optimization of compositional microprogram control units with sharing of codes. Avtomatizacija proektirovanija diskretnych sistem, vol 1, Minsk, Białoruś, 2004, pp. 16-22.
83. R. Wiśniewski, A. Barkalov, L. Titarenko: Optimization of address circuit of compositional microprogram unit. Proceedings of EWDTW '06, Sochi, Rosja, 2006, pp. 167-170.
84. A. Barkalov, L. Titarenko, R. Wiśniewski: Optimization of the circuit of compositional microprogram control unit with mutual memory. Proceedings of CADSM 2007, Lviv -Polyana, Ukraina, 2007, pp. 251-255.
85. A. Barkalov, K. Efimenko, R. Wiśniewski: Optimizacia shemy adresacii kompozicionnogo ustrojstva upravlenia. Naukovi Praci DNTU: Probierni Modeljuvannja ta Avtomatizacii Proektuvannja Dinamicnich Sistem, Doneck, Ukraine, no 5, 2006, pp. 156-161.
86. A. Barkalov, R. Wiśniewski: Optimization of compositional microprogram control units implemented on system-on-chip. Informatyka Teoretyczna i Stosowana, no 9, 2005, pp. 7-22.
87. R. Wiśniewski: Design of compositional microprogram control units with elementary operational linear chains. Proceedings of DESDes '06, Rydzyna, Polska, 2006, pp. 191-194.
88. A. Barkalov, R. Wiśniewski, S. Kovalyov, K. Efimenko: Optimizacia eisla LUT-elementov v ustrojstve upravlenia sistemy na kristalle. Sbornik trudov XIII medunarodnoj naucno-tehniceskoj konferencii, vol. 1, Sevastopol, Ukraine, 2006, pp. 75-80.
89. A. Barkalov, R. Wiśniewski: Optimization of compositional microprogram control units with sharing of codes. Avtomatizacija proektirovanija diskretnych sistem: materiały pjatoj mezdunarodnoj konferencii; vol. 1, Minsk, Białoruś, 2004, pp. 16-22.
90. R. Wiśniewski: Design of compositional microprogram control units with sharing of the codes. Proceedings of OWD 2004; vol. 19, Wisła, Poland, 2004, pp. 217-220.
91. R. Wiśniewski: Synteza mikroprogramowanych układów sterujących ze współdzieleniem kodów z wykorzystaniem dekodera adresów. Pomiary Automatyka Kontrola, no 6, 2006, ss. 38-40.
92. R. Wiśniewski, A. Barkalov, L. Titarenko: Synthesis of compositional microprogram control units with sharing codes and address decoder. Proceedings of MIXDES 2006, Gdynia, Polska, 2006, pp. 397-400.
93. IEEE Standard Verilog Hardware Description Language 1364-2001. New York, 2001.
94. D. Thomas, P. Moorby: The Verilog hardware description language. Kluwer Academic Publishers, Norwell, MA, USA, 5th edition, 2002.

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