High level synthesis in EDA tool "Abelite"

• Autorzy: Baranov S.
• Konferencja: Digital Control Units Design ; 6.03.2009 ; Zielona Góra, Poland
• Języki publikacji: EN

Abstrakty

EN

The paper presents the first description of methods and algorithms realized in experimental EDA tool Abelite. High level synthesis, implemented in this tool is based on Algorithmic State machine (ASM) transformations (composition, minimization, extraction, etc.), special algorithms for Data Path and Control Unit design and a very fast optimizing synthesis of FSM and combinational circuits with hardly any constraints on the number of inputs, outputs and states. Design tools supporting this methodology allow very fast to implement, check and estimate many possible design versions, to find an optimized decision of the design problem and to simplify the verification problem for digital systems.

Słowa kluczowe

EN

EDA tools; high level synthesis; logic synthesis; VHDL

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: Electronics and Telecommunications Quarterly
• Rocznik: 2009
• Tom: Vol. 55, No 2
• Strony: 123--156
• Opis fizyczny: tab., wykr.

Twórcy

autor

Baranov S.

• Holon Institute of Technology, Dept. of Computer Sc., Holon, Israel,