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SystemC-based codesign of distributed embedded systems

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Języki publikacji
EN
Abstrakty
EN
Most of existing co-synthesis methods for embedded systems requires a task graph model of a system. This work presents a codesign methodology for embedded systems specified using SystemC language. For each system specification, developed according to this methodology, it is possible to automatically generate the task graph or the conditional task graph corresponding to this specification. To simplify the codesign process and to reduce the time required to develop the specification, a framework in the form of a library built on top of the SystemC language core was created. This library contains definitions of communication channels, interfaces, ports and macros implementing a model of computation corresponding to the task graph semantics. Benefits of the presented methodology were demonstrated by comparing synthesis results of the same system, represented by different SystemC models and using our co-synthesis methods for SOC, SOPC and dynamically reconfigurable SOPC systems.
Rocznik
Strony
71--93
Opis fizyczny
Bibliogr. 33 poz., tab., wykr.
Twórcy
autor
autor
Bibliografia
  • 1. IEEE Standard SystemC Language Reference Manual, IEEE, New York, 2006.
  • 2. R. P. Diek, N. K. Jha: CORDS: Hardware-Software Co-synthesis of Reconfigurable Real-time Distributed Embedded Systems, Proc. ICCAD, 1998, pp.62-68.
  • 3. K. B. Chehida, M. Auguin: HW/SW Partitioning Approach for Reconfigurable System Design, Proc. CASES 2002, 2002, pp. 247-251.
  • 4. K. S. Chatha, R. Vemuri: Hardware-software codesign for dynamically reconfigurable architectures, Proc. FPL, 1999, pp. 175-184.
  • 5. S. Banerjee, E. Bozorgzadeh, N. Dutt: Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration, Proc. DAC, 2005, pp. 335-340.
  • 6. Y. Qu, J.-P. Soininen, J. Nurmi: A Paralel Configuration Model for Reducing the Run-time Reconfiguration Overhead, Proc. DATE'06, 2006, pp. 965-969.
  • 7. W. Wolf: High-Performance Embedded Computing: Architectures, Applications, and Methodologies, Morgan Kaufman, 2006.
  • 8. A. Daboli, P. Eles: Scheduling Under Data and Control Dependencies for Heterogeneous Architectures, Proc. of the International Conference on Computer Design, 1998, pp. 602-608.
  • 9. Y. Xie, W. Wolf: Allocation and Scheduling of Conditional Task Graph in Hardware/Software Co-synthesis, Proc. DATE, 2001, pp. 620-625.
  • 10. D. Wu, B. M. Al-Hashimi, P. Eles: Scheduling and mapping of conditional task graph for the synthesis of low power embedded systems, IEEE Proceedings Computers and Digital Techniques, 2003, Vol. 150 Issue: 5 pp. 262-273.
  • 11. Y. Xie, L. Li, M. Kandemir, et al.: Reliability-aware co-synthesis for embedded systems, Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, 2007, Vol. 49, Issue: 1, pp. 87-99.
  • 12. P. Eles, K. Kuchcinski, Z. Peng, A. Doboli, P. Pop: Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems, Proc. of the IEEE DATE Conf., 1998, pp. 132-138.
  • 13. K. S. Vallerio, N. K. Jha: Task Graph Extraction for Embedded System Synthesis, Proc. IEEE Int. Conference on VLSI Design, 2003, pp. 480-486.
  • 14. S. A. Khayam, S. A. Khan, S. Sadiq: A Generic Integer Programming Approach to Hardware/Software Codesign, Proc. of IEEE International Multi Topic Conference IEEE INMIC 2001. Technology for the 21st Century, 200, pp. 6-9.
  • 15. R. P. Dick, N. K. Jha: MOGAC: A multiobjective Genetic Algorithm for the Co-Synthesis of Hardware-Software Embedded Systems, Proc. of the International Conference on Computer Aided Design, IEEE Computer Society Press, Los Alamitos, 1997, pp. 522-529.
  • 16. B. P. Dave, G. Lakshminarayana, N. K. Jha: COSYN: Hardware-Software Co-Synthesis of Embedded Systems, Proc. of the 34th Design Automation Conference. ACM Press, New York, 1997, pp. 703-708.
  • 17. T.-Y. Yen, W. H. Wolf: Sensitivity-Driven Co-Synthesis of Distributed Embedded Systems, Proc.of International Symposium on System Synthesis, 1995, pp. 4-9.
  • 18. R. P. Dick, N. K. Jha: MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis, Proc. of the Conference on Design Automation and Test in Europe. IEEE Computer Society Press, Los Alamitos, 1999, pp. 263-270.
  • 19. L. Shang, R. P. Dick, N. K. Jha: SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, pp. 508-526.
  • 20. J. Ou, S. B. Choi, V. K. Prasanna: Energy-Efficient Hardware/Software Co-synthesis for a Class of Applications on Reconfigurable SoCs, International Journal of Embedded Systems, 2005, Vol. 1, No. 1/2, pp. 91-102.
  • 21. F. Ferrandi, M. D. Santabrogio, D. Sciuto: A Design Methodology for Dynamic Reconfiguration: The Coronte Architecture, 19th IEEE International Parallel and Distributed Processing Symposium - Workshop 3, 2005, pp. 163-166.
  • 22. M. T. Schmitz, B. M. Al-Hashimi, P. Eles: Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems, Proc. of the Conference on Design Automation and Test in Europe. IEEE Computer Society Press, Los Alamitos, 2002, pp. 514-521.
  • 23. A. Ross, S. Swan, J. Pierce, J.-M.: Fernandez: Transaction Level Modeling in SystemC, www.systemc.org.
  • 24. A. Donlin: Transaction Level Modeling: Flows and use models, Proc. CODES+ISSS'04, 2004, pp. 75-80.
  • 25. H. Herrera, P. Sanchez, E. Villar: Modeling and Design of CSP, KPN and SR Systems with SystemC, in C. Grimm (ed.) Languages for System Specification, Kluwer, 2004.
  • 26. H. Herrera, E. Villar: A Framework for Embedded System Specification under Different Models of Computation in SystemC, Proc. IEEE/ACM Design Automation Conf., 2006, pp. 911-914.
  • 27. J. Falk, C. Haubell, J. Teich: Efficient Representation and Simulation of Model-Based Designs in SystemC, Proc. Forum on Design Languages, 2006, pp. 129-134.
  • 28. C. Haubelt.J. Falk,J. Keinert,T. Schlichter, M. Streubühr, A. Deyhle, A. Hadert, J. Teich: A SystemC-based Design Methodology for Digital Signal Processing Systems, EURASIP Journal on Embedded Systems, March 2007.
  • 29. J. Henkel, R. Ernst: High-level estimation techniques for usage in hardware/software co-design, Proc. Asia and South Pacific Automation Conference, 1998, pp. 353-360.
  • 30. S. Deniziak: Cost-Efficient Synthesis of Multiprocessor Heterogeneous Systems, Control and Cybernetics, 2004, Vol. 33, No. 2, pp. 341-355.
  • 31. R. Czarnecki: Kosynteza dynamicznie samorekonfigurowalnych systemów wbudowanych, PhD Thesis, 2008, p. 123, (In Polish).
  • 32. Xilinx Inc.: Two flows for partial reconfiguration: module based or difference based, Xilinx Application Note XAPP290, v.1.2, 2004.
  • 33. R. Czarnecki, S. Deniziak: Co-Synthesis of Dynamically Reconfigurable SOPCs Specified by Conditional Task Graphs, The Open Cybernetics and Systemics Journal, 2008, Vol. 2, pp. 206-218.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BWA0-0037-0022
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