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A Token-ManagedAdmission Control (TMAC) mechanism is introduced in order to provide efficient Quality-of-Service (QoS) support for different types of application on a best-effort Globally-Asynchronous Locally-Synchronous (GALS) interconnect fabric. The mechanism is applied at the ingress edges of the fabric using tokens to allocate dynamic network resources and prevent network congestion. The degree of fairness is controllable, in order to balance the desired throughput and data transfer resource allocation appropriately for a particular application. The simulation and analysis presented here shows efficient QoS provision. Our detailed implementation and analysis show that TMAC provides service guarantees on the network while using a modest physical area because of the simplicity of the control logic.
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Czasopismo
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Tom
Strony
53--72
Opis fizyczny
Bibliogr. 36 poz., wykr.
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autor
autor
autor
autor
- School of Computer Science, The University of Manchester, Oxford Road, Manchester M139PL, yangsa@cs.man.ac.uk
Bibliografia
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- [5] Bahn, J. H., Lee, S. E., Bagherzadeh, N.: On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture, ITNG, 2007.
- [6] Bainbridge, J., Furber, S. B.: Delay insensitive System-on-Chip Interconnect Using 1-of-4 Data Encoding, Proceeding ASYNC 2001, 2001.
- [7] Bainbridge, J., Furber, S. B.: CHAIN: A Delay-Insensitive Chip Area Interconnect, IEEE Micro, 22(5), 2002, 16-23, ISSN 0272-1732.
- [8] Bainbridge, W. J., Furber, S. B.: Asynchronous Macrocell Interconnect using MARBLE, ASYNC '98: Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society,Washington, DC, USA, 1998, ISBN 0-8186-8392-9.
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- [15] Chapiro, D.: Globally Asynchronous Locally Synchronous Systems, Ph.D. Thesis, Stanford University, 1984.
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- [17] Felicijan, T.: Quality-of-Service (QoS) for Asynchronous On-Chip Networks, Ph.D. Thesis, University of Manchester, School of Computer Science, 2004.
- [18] Felicijan, T., Bainbridge,W. J., Furber, S. B.: An Asynchronous Low Latency Arbiter for Quality of Service (QoS) Applications, Proceedings of the 15th International Conference on Microelectronics (ICM'03), Cairo, Egypt, December 2003, ISBN 9770520101.
- [19] Furber, S. B.: Future Trends in SoC Interconnect, Proc. IEEE International Symposium on Design, Automation and Test (VLSI-TSA-DAT), Hsinchu,TaiWan, 2005.
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- [21] Furber, S. B., Temple, S., Brown, A.: On-Chip and Inter-Chip networks for Modelling Large-Scale Neural Systems, International Symposium on Circuits and Systems, ISCAS-2006, Kos, Greece, 21-24 May 2006, ISBN 0-7803-9390-2.
- [22] Goossens, K., Dielissen, J., van Meerbergen, J., Poplavko, P., R˘adulescu, A., Rijpkema, E., Waterlander, E., Wielage, P.: Guaranteeing the quality of services in networks on chip, 2003, 61-82.
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- [24] Guz, Z., Walter, I., Bolotin, E., Cidon, I., Ginosar, R., Kolodny, A.: Efficient Link Capacity and QoS Design for Network-on-Chip, Proc. Design, Automation and Test in Europe (DATE), Mar 2006.
- [25] Millberg, M., Jantsch, A.: A Study of NoC Exit Strategies, In Proc. of the ACM/IEEE Int. Symp. on Networkson-Chip (NOCS), 2007.
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- [28] Plana, L. A., Furber, S. B., Temple, S., Khan, M., Shi, Y., Wu, J., Yang, S.: A GALS Infrastructure for a Massively Parallel Multiprocessor, IEEE Design & Test of Computers, 24(5), Sept. 2007, 454-463.
- [29] Rast, A. D., Yang, S., Khan, M., Furber, S. B.: Virtual Synaptic Interconnect Using an Asynchronous Network-on-Chip, Proc. 2008 Int'l Joint Conf. on Neural Networks (IJCNN2008), Jun 2008.
- [30] Rijpkema, E., Goossens, K. G.W., R˘adulescu, A., Dielissen, J., vanMeerbergen, J.,Wielage, P.,Waterlander, E.: Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip, in: Design Automation, and Test in Europe. The Most Influential Papers of 10 Years DATE, Springer, 2008, 350-355.
- [31] Saulsbury, A., Pong, F., Nowatzyk, A.: Missing the memory wall: the case for processor/memory integration, ISCA '96: Proceedings of the 23rd annual international symposium on Computer architecture, ACM, New York, NY, USA, 1996, ISBN 0-89791-786-3.
- [32] Silistix, L.: Building and Analyzing On-Chip Networks using CHAINarchitect, Technical Report V1.0, http://www.silistix.com, DEC 2007.
- [33] Tedesco, L.,Mello, A., Garibotti, D., Calazans, N.,Moraes, F.: Traffic generation and performance evaluation for mesh-based NoCs, SBCCI '05: Proceedings of the 18th annual symposium on Integrated circuits and system design, ACM, New York, NY, USA, 2005, ISBN 1-59593-174-0.
- [34] Tran, X.-T, D., J, Thonnart, Y.: Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip, First International Symposium on Networks-on-Chip, May 2007.
- [35] Vellanki, P., Banerjee, N., Chatha, K. S.: Quality-of-service and error control techniques for mesh-based network-on-chip architectures, Integration, 38(3), 2005, 353-382.
- [36] Walter, I., Cidon, I., Ginosar, R., Kolodny, A.: Access regulation to hot-modules in wormhole NoCs, Proc. of the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), May 2007.
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Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BUS8-0005-0072