Application of Concurrency in the Asynchronous Design of Write-after-read Operations

• Autorzy: Toosizade N. , Zaky S.G.
• Języki publikacji: EN

Abstrakty

EN

This paper introduces enhancements to the synthesis of circuits that involve write-afterread (WAR) operations and use the four-phase handshake protocol. The paper demonstrates that the use of edge-triggering makes possible many useful trade-offs among speed, area and powerdelay product. Significant increases in speed are possible as a result of increased concurrency in the circuit's operation, which compensates for much of the penalty associated with the down phase of the four-phase protocol. It is also shown that concurrency can be increased by the judicious insertion of T-elements in the system's control structure. Simulation results for a 16-bit accumulator showed a speed increase of 50% and a reduction of 23% in the power-delay product. The speed of a radix-4 Booth multiplier increased by over 27% and its area and energy consumption were reduced by 5%. These results were derived using test circuits synthesized by Balsa and implemented in Synopsys using 180-nm technology.

Słowa kluczowe

EN

write-after-read operation; asynchronous circuits; syntax-directed compilation; sequencer; S-element; T-element; handshake circuits; handshake components; concurrency

• Wydawca: IOS Press
• Czasopismo: Fundamenta Informaticae
• Rocznik: 2009
• Tom: Vol. 95, nr 1
• Strony: 31--52
• Opis fizyczny: Bibliogr. 14 poz., wykr.

Twórcy

autor

Toosizade N.

autor

Zaky S.G.

• The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, Toronto, Ontario, M5S 3G4, Canada,

Bibliografia

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