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Detecting State Encoding Conflicts in STG Unfoldings Using SAT

Wybrane pełne teksty z tego czasopisma
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Warianty tytułu
Konferencja
Third International Conference on Application of Concurrency to System Design (ACSD'03) (18-20 June, 2003, Guimaraes, Portugal)
Języki publikacji
EN
Abstrakty
EN
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is that of identifying whether an STG satisfies the Complete State Coding (CSC) requirement (which states that semantically different reachable states must have different binary encodings), and, if necessary, modifying the STG (by, e.g., inserting new signals helping to trace the current state) to meet this requirement. This is usually done using reachability graphs. In this paper, we avoid constructing the reachability graph of an STG, which can lead to state space explosion, and instead use only the information about causality and structural conflicts between the events involved in a finite and complete prefix of its unfolding. We propose an efficient algorithm for detection of CSC conflicts based on the Boolean Satisfiability (SAT) approach. Following the basic formulation of the state encoding conflict relationship, we present some problem-specific optimization rules. Experimental results show that this technique leads not only to huge memory savings when compared to the CSC conflicts detection methods based on reachability graphs, but also to significant speedups in many cases.
Wydawca
Rocznik
Strony
221--241
Opis fizyczny
Bibliogr. 38 poz., tab., wykr.
Twórcy
autor
  • School of Computing Science, University of Newcastle, Newcastle upon Tyne NE1 7RU, U.K.
autor
  • School of Computing Science, University of Newcastle, Newcastle upon Tyne NE1 7RU, U.K.
autor
  • School of Electrical, Electronic and Computer Engineering, University of Newcastle, upon Tyne NEl 7RU, United Kingdom
Bibliografia
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  • [41 Chu, T.-A.: Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications, Ph.D. Thesis, Laboratory for Computer Science, Massachusetts Institute of Technology, 1987.
  • [5] Cortadella, J., Kishinevsky, M., Kondratyev, A., Lavagno, L., Yakovlev, A.: Complete State Encoding Based on Theory of Regions, Proc. ASYNC'1996, IEEE Computer Society Press, 1996.
  • [6] Cortadella, J., Kishinevsky, M., Kondratyev, A., Lavagno, L., Yakovlev, A.: PETRIFY: a Tool tor Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers, lEICE Transactions on information and Systems, E80-D(3), 1997, 315-325.
  • [7] Cortadella. J., Kishinevsky. M., Kondratyev, A., Lavagno, L., Yakoviev, A.: Logic Synthesis of Asynchronous Controllers and Interfaces. Springer-Verlag, 2002.
  • [8] Engelfriet, J.: Branching Processes of Petri Nets, Acta Informatica, 28. 1991. 575-591.
  • [9] Esparza, J.: Decidability and Complexity of Petri Net Problems — an Introduction, Lectures on Petri Nets I.- Basic Models (W. Reisig, G. Rozenberg, Eds.). Lecture Notes in Computer Science 1491, Springer-Verlag, 1998.
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  • [16] Khomenko, V, Koutny, M., Yakovlev. A.: Detecting State Coding Conflicts in STGs Using Integer Programming, Proc. DATE'2002 (C. Kloos, J. Franca, Eds.), IEEE Computer Society Press. 2002.
  • [17] Khomenko, V. Koutny, M., Yakovlev, A.: Detecting State Coding Conflicts in STG Unfoldings Using SAT. Proc. ICACSD '2003 (J. Lilius, F Balarin. R. Machado, Eds.). IEEE Computer Society Press, 2003.
  • [18] Kishinevsky, M., Kondratyev, A., Taubin, A., Varshavsky, V: Concurrent Hardware: The Theory and Practice of Self-Timed Design, Series in Parallel Compufing, John Wiley & Sons, Inc., New York. USA, 1994.
  • [19] Kondratyev, A., Cortadella, J., Kishinevsky, M., Lavagno, L., Taubin. A., Yakovlev, A.: Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings. Proc. ICACSD' 1998, IEEE Computer Society Press, 1998.
  • [20] Kondratyev, A., Cortadella. J., Kishinevsky, M., Pastor, E., Roig. O., Yakovlev, A.: Checking Signal Transition Graph Implementability by Symbolic BDD Traversal, Proc. DATE'1995, IEEE Computer Society Press, 1995.
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  • [22] Lin, K.-J., Kuo, J.-W., Lin. C.-S.: Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and MG-Decomposition Approach, Proc. of EDTC'1994, IEEE Computer Society Press, 1994.
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  • [27] McMillan. K.: Symbolic Model Checking: an Approach to the State Explosion Problem, Ph.D. Thesis, School of Computer Science, Carnegie Mellon University, 1992.
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  • [29] Moskewicz, S., Madigan, C, Zhao, Y, Zhang. L., Malik, S.: CHAFF: Engineering an Efficient SAT Solver, Proc. DAC'2001, ACM Technical Publishing. 2001.
  • [30] Pastor, E., Cortadella, J.: Polynomial Algorithms for the Synthesis of Hazard-free Circuits from Signal Transition Graphs, Proc. of ICCAD'1993, IEEE Computer Society Press, 1993.
  • [31] Pastor, E., Cortadella, J., Roig, O.: Symbolic Analysis of Bounded Petri Nets, IEEE Transactions on Computers, 50(5), 2001, 432-448.
  • [32] Semenov, A.: Verification and Synthesis of Asynchronous Control Circuits Using Petri Net Unfolding, Ph.D. Thesis, Department of Computing Science, University of Newcastle upon Tyne, 1997.
  • [33] Semenov, A., Yakovlev, A., Pastor, E., Pefla, M., Cortadella, J., Lavagno, L.: Partial Order Approach to Synthesis of Speed-Independent Circuits, Proc. ASYNC'1997, IEEE Computer Society Press, 1997.
  • [34] Vanbekbergen, P., Catthoor, R, Goossens. G., De Man, H.: Optimized Synthesis of Asynchronous Control Circuits from Graph-Theoretic Specifications, Proc. ICCAD'J990. IEEE Computer Society Press, 1990.
  • [35] Yakovlev, A.: Designing Control Logic for Counterflow Pipeline Processor Using Petri nets, Formal Methods in System Design, 12(1), 1998,39-71.
  • [36] Yakovlev, A., Lavagno, L., Sangiovanni-Vincentelli, A.: A Unified Signal Transition Graph Model for Asynchronous Control Circuit Synthesis, Formal Methods in System Design, 9(3), 1996, 139-188.
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Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BUS2-0005-0079
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