Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation

• Autorzy: Garnica O. , Lanchares J. , Hermida R.
• Języki publikacji: EN

Abstrakty

EN

This paper is devoted to studying two key issues of the asynchronous pipelines: their performance, and the influence that the position of stages have on the latency of a pipelined asynchronous circuit as a whole. To attain the performance evaluation, we derive expressions of the latency and the cycle time of a linear pipeline as closed-form formulas. To attain the influence of the position, we present some experiments, using the previous closed-form formulas, on different pipelines.

Słowa kluczowe

EN

asynchronous circuitis; pipeline performance

• Wydawca: IOS Press
• Czasopismo: Fundamenta Informaticae
• Rocznik: 2002
• Tom: Vol. 50, nr 2
• Strony: 155--174
• Opis fizyczny: tab., wykr., bibliogr. 14 poz.

Twórcy

autor

Garnica O.

autor

Lanchares J.

autor

Hermida R.

• Department of Computer Architecture, Universidad Complutense de Madrid, 28040 Madrid, Spain,