System-level approaches to power efficiency in FPGA-based designs (data reduction algorithms case study)

• Autorzy: Czapski P. P. , Śluzek A.
• Języki publikacji: EN

Abstrakty

EN

In this paper we present preliminary results on systemlevel analysis of power efficiency in FPGA-based designs. Advanced FPGA devices allow implementation of sophisticated systems (e.g. embedded sensor nodes). However, designing such complex applications is prohibitively expensive at lower levels so that, moving the designing process to higher abstraction layers, i.e. system-levels of design, is a rational decision. This paper shows that at least a certain level of power awareness is achievable at these higher abstractions. A methodology and preliminary results for a power-aware, system-level algorithm partitioning is presented. We select data reduction algorithms as the case study because of their importance in wireless sensor networks (WSN's). Although, the research has been focused on WSN applications of FPGA, it is envisaged that the presented ideas are applicable to other untethered embedded systems based on FPGA's and other similar programmable devices.

Słowa kluczowe

EN

power awareness; FPGA; system-level; Handel-C; data reduction

• Wydawca: Łukasiewicz Industrial Research Institute for Automation and Measurements PIAP
• Czasopismo: Journal of Automation Mobile Robotics and Intelligent Systems
• Rocznik: 2011
• Tom: Vol. 5, No. 2
• Strony: 49--59
• Opis fizyczny: Bibliogr. 48 poz., rys.

Twórcy

autor

Czapski P. P.

autor

Śluzek A.

• Nanyang Technological University, School of Computer Engineering, Block N4 #02a-32, NanyangAvenue, Singapore 639798,

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