Metody obniżania poboru mocy podczas testowania wewnątrzukładowego

• Autorzy: Puczko M.

Warianty tytułu

EN

Low power in BIST

• Języki publikacji: PL

Abstrakty

PL

W referacie przedstawiono wyniki badań nad obniżeniem rozpraszanej mocy generatora pseudolosowych wektorów testowych i analizatora sygnatur, które są wykorzystywane podczas wbudowanego samotestowania urządzeń cyfrowych BIST (ang. Built-In Self-Testing). Zaproponowano nową strukturę układu, która pozwala obniżyć moc wydzielaną w trakcie przeprowadzania samotestowania. Główna idea opiera się na takiej modyfikacji elementów BIST, w której zamiast przerzutników -D wykorzystuje się przerzutniki -T.

EN

Nowadays during organizing built-in self testing the most spread and best known are scan design techniques based on the full or partly scanning path. The first testing vector is put into testing system by SP (Scanning Path) data. Shifting information takes place during clock pulses, and the number of shifts is equal to the number of flip-flops in SP. Then, one synchronization pulse is used to write system changes in adequate SP positions. Next, SP values are applied to the output of the circuits, and at the same time on the date input SP follow next testing vector. So, if the SP is built of k-elements, there are needed k+1 clock pulses to put one testing vector. This realization is non effective because of high power consumption. Firstly, in modern BIST systems there are used many D-flip flops (memory elements). Even when there are used many SPs, the number of positions in each SP can reach a few thousands. In this case to put a new testing vector it is necessary to use a few thousand of synchronization pulses. Simultaneously the high amount of energy is needed, because each new testing vector needs one synchronization pulse. Secondly, during shifting data in SP in a testing circuit there are empty switchings, which requires energy. So, to minimize the power consumption test-per-clock technique is used. In this paper the new idea of minimizing power dissipation in BIST with test-per-clock technique is presented. The main idea of the new solution is to stop putting synchronization pulses to flip-flops in which their state has not changed in the current synchronization pulses. It will allow eliminating not necessary switching activity in BIST and, what is more, it will allow to decrease power consumption and Weighted Switching Activity.

Słowa kluczowe

PL

niski pobór mocy; test-per-clock; BIST; przerzutnik -T; przerzutnik D

EN

low power BIST; flip-flop-T; test-per-clock; BIST; flip-flop-D

• Wydawca: Wydawnictwo PAK
• Czasopismo: Pomiary Automatyka Kontrola
• Rocznik: 2009
• Tom: R. 55, nr 8
• Strony: 672--674
• Opis fizyczny: Bibliogr. 10 poz., rys., tab., wzory

Twórcy

autor

Puczko M.

• Wydział Informatyki, Politechnika Białostocka,

Bibliografia

• [1] Yeap G. P.: Practical Low Power Digital VLSI Design, Kluwer Academic Publisher, 1998.
• [2] Zorian Y.: A Distributed BIST Control Scheme for Complex VLSI Dissipation, Proceedings of IEEE VLSI Symposium, 1993, pp. 4-9.
• [3] Stroud C. E.: A Designer’s Guide to Built-In Self Test, Boston/ Dordrecht/ London, Kluwer Academic Publisher, 2002.
• [4] Ravikumar C. P., Prasad N.S.: Evaluating BIST architectures for low power // Proceedings of 7th Asian Test Symposium, 1998, 430-434.
• [5] Murashko I., Puczko M.; The switching activity minimization for Low Power BIST, In book “Computer Information Systems and Industrial Management Applications”, Editors K. Saeed, R. Mosdorf, Z. Sosnowski, O. P. Hilmola, Bialystok, Poland, pp. 218-225.
• [6] Yarmolik V. N., Murashko I.: A new idea for testing vector generation in BIST // Avtomatika I Vychislitelnaja Tecnika, 1995, N6, pp. 25-35.
• [7] Yarmolik V. N., Murashko I., Schmigman A. M.: Analyzing and designing scanning path for BIST, Microelectronika, 1997, T. 26, No 5, pp. 350-353.
• [8] Murashko I. A., Yarmolik V. N., Schmigman A. M.: A new idea for designing scanning paths in BIST, Automatic and Telemachanics, 1998, N7, pp. 157-167.
• [9] Puchalski G. I., Nowoselcewa T. Y.; Designing digital devices based on integrated circuit, Moscow, Radio i Svjas’, 1990.
• [10] Golomb S. W.: Shift Registers sequences – Holden Day, San Francisco, 1967.