Dynamicznie rekonfigurowalny sterownik logiczny - łatwo programowalna architektura

• Autorzy: Milik A.

Warianty tytułu

EN

Dynamically reconfigurable logic controller - architecture of improved programmability

• Języki publikacji: PL

Abstrakty

PL

Artykuł przedstawia architekturę sterownika bitowego implementowanego w strukturze FPGA umożliwiającego wyeliminowanie złożonego procesu implementacji poprzez wykorzystanie odpowiedniej struktury sprzętowej i narzędzi programowania.

EN

The paper presents an idea of a Programmable Logic Controller for binary control implemented in an FPGA device with use of custom designed architecture and implementation tools. The solution does not require vendor synthesis and implementation tools except for final bitstream generation. It is an extension of the previously proposed architecture (Figs. 1 and 2). The architecture is based on a hardwired set of connections that is formed inside the FPGA device žLC units. The žLC can be programmed by means of LUT table modification. The architecture is mainly limited by the hardwired connection that bases on an invariant set of multiplexed signals delivered to the žLC. A new architecture is proposed, extending programmability of the architecture to programmable connections which are available in FPGAs (Figs. 3 and 4). The žLC architecture has also been modified and exactly fitted into the regular structure of an FPGA (Fig. 5). The new logic resources supplementing architecture modifications of the controller has been defined. They are input (Fig. 6) and output (Fig. 7) cells. The possible computation capabilities of FPGA devices are gathered in Tab. 1. The research task is in progress. A new solution with extended use of programmable connections, better exploitation of logic resources and easiness of logic synthesis and programming is searched for.

Słowa kluczowe

PL

sterownik programowalny; rekonfiguracja dynamiczna; FPGA; synteza logiczna

EN

PLC; FPGA; dynamic reconfiguration; logic synthesis

• Wydawca: Wydawnictwo PAK
• Czasopismo: Pomiary Automatyka Kontrola
• Rocznik: 2009
• Tom: R. 55, nr 8
• Strony: 587--590
• Opis fizyczny: Bibliogr. 7 poz., rys., tab., wzory

Twórcy

autor

Milik A.

• Instytut Elektroniki, Politechnika Śląska,

Bibliografia

• [1] A. Milik: High Level Synthesis – Reconfigurable Hardware Implementation of Programmable Logic Controller, PDeS 2006 Programable Devices and Embedded Systems, Brno 14-16 February 2006.
• [2] M. Chmiel, E. Hrynkiewicz, A. Milik: Remarks on Improving of Operation Speed of The PLCs, 16th IFAC World Congress, Prague, 4-8 July 2005.
• [3] E. Hrynkiewicz, A. Milik, J. Mocha: Dynamicznie rekonfigurowana współbieżna realizacja sterowania binarnego, VII Krajowa Konf. Elektroniki, Darłowko Wsch. 2-4 Czerw. 2008.
• [4] C. Claus, B. Hang, M. Hubner, C. Schmutzler, J. Becker, W. Stechele: An XDL-based busmacro generator for customizable communications interfaces for dynamically and partially reconfigurable systems, RC Education, Porto Allegre, Brasil, May 2007.
• [5] A. Ehliar, D. Liu: Thinking Outside the Flow: Creating Customized Backend Tools for Xilinx Based Designs, FPGA World 2007, Stockholm, Sweden, September 2007.
• [6] N. Sedcole PhD Dissertation: Reconfigurable Platform-Based Design in FPGAs for Video Image Processing, University of London, January 2006.
• [7] Xilinx: XAPP 151: Virtex Series Configuration Architecture User Guide, v. 1.5 09.2000.