Synteza odwracalnych układów logicznych

• Autorzy: Kerntopf P.

Warianty tytułu

EN

Synthesis of reversible logic circuits

• Języki publikacji: PL

Abstrakty

PL

Opracowywanie metod syntezy binarnych odwracalnych układów logicznych rozpoczęto niedawno. Artykuł zawiera krótki przegląd publikacji na ten temat, w tym wyniki autora.

EN

The development of synthesis methods for binary reversible logic circuits has started recently. The paper presents a brief survey of publications on the topic including the author's results.

Słowa kluczowe

PL

odwracalne bramki logiczne; algorytmy syntezy odwracalnych układów

EN

reversible logic gates; algorithms for reversible circuit synthesis

• Wydawca: Wydawnictwo PAK
• Czasopismo: Pomiary Automatyka Kontrola
• Rocznik: 2007
• Tom: R. 53, nr 7
• Strony: 78--80
• Opis fizyczny: Bibliogr. 19 poz., rys., tab., wzory

Twórcy

autor

Kerntopf P.

• Instytut Informatyki, Politechnika Warszawska,

Bibliografia

• [1] C. H. Bennett, Notes on the history of reversible computation, IBM Journal of Research and Development, 1988, vol. 30, pp. 16-23.
• [2] V. V. Shende, A. K. Prasad, I. L. Markov, J. P. Hayes, Synthesis of reversible logic circuits, IEEE Trans. on Computer-Aided Design, 2003, vol. 22, no 6, pp. 710-722.
• [3] M. P. Frank, Reversibility for efficient computing, Ph. D. Thesis, Massachussets Institute of Technology, Cambridge, MA, USA, 1999.
• [4] P. Kemtopf, On universality of binary reversible logic gates, Proc. 5th Int. Workshop on Boolean Problems, Freiberg, Niemcy, 2002, pp. 47-52.
• [5] A. De Vos, L. Storme, All non-linear reversible logic gates are r-universal, Proc. 6th hit. Workshop on Boolean Problems, Freiberg, Niemcy, 2004, pp. 25-31.
• [6] P. Kemtopf, M. A. Perkowski, M. B. A. Khan, On universality of general reversible multiple-valued logic gates, Journal of Multiple-Valued Logic and Soft Computing, 2006, vol. 12, no 5-6, pp. 717-429.
• [7] A. Mishchenko, M. Perkowski, Logic synthesis of reversible wave cascades, Proc. 11th IEEE/ACM Workshop on Logic and Synthesis, New Orleans, USA, 2002, pp. 197-202.
• [8] A. Agrawal, N. K. Jha, Synthesis of reversible logic, Proc. Design Automation & Test in Europe Conference, Feb. 2004, pp. 21384-21385.
• [9] P. Gupta, A. Agrawal, N. K. Jha, An algorithm for synthesis o reversible logic circuits, IEEE Trans. on Computer-Aided Design, 2006, vol. 25, pp. 2317-2330.
• [10] D. M. Miller, D. Maslov, G. W. Dueck, A transformation based algorithm for reversible logic synthesis, Proc. 40th Design Automation Conference, ACM, Anaheim, CA, USA, 2003, pp. 318-323.
• [11] D. Maslov, G. W. Dueck, D. M. Miller, Fredkin/Tofoli templates for reversible logic synthesis, Proc. Int. Conference on Computer-Aided Design, ACM, San Jose, CA, USA, 2003, pp. 256-261.
• [12] P. Kemtopf, Reversible logic circuit synthesis based on a new complexity measure, Proc. 13th IEEE/ACM Workshop on Logic and Synthesis, Temecula, USA, 2004, pp. 106-113.
• [13] P. Kemtopf, A new heuristic algorithm for reversible logic circuit synthesis, Proc. 41st Design Automation Conference, ACM, San Diego, USA, 2004, pp. 834-837.
• [14] P. Kemtopf, An approach to synthesis of multiple-valued reversible logic circuits, Proc. 6th Int. Workshop on Boolean Problems, Freiberg, Niemcy, 2004, pp. 33-40.
• [15] P. Kemtopf, Some remarks on reversible logic synthesis, Proc. 8th Int. Workshop on Representations and Methodology of Future Computer Technology, Oslo, 2007.
• [16] M. Perkowski, P. Kemtopf, A. Coppola, A. Buller, M. Chrzanowska-Jeske, A. Mishchenko, Xiaoyu Song, A. Al-Rabadi, L. Jóźwiak B. Massey, Regularity and symmetry as a base for efficient realization of reversible logic circuits, Proc. 10th IEEE/ACM Workshop on Logic and Synthesis, Granlibakken, CA, USA, 2001, pp. 90-95.
• [17] G. Negovetovic, M. Perkowski, M. Lukar, A. Buller, Evolving quantum circuits and an FPGA-based quantum computing emulator, Proc. 5th Int. Workshop on Boolean Problems, Freiberg, Niemcy, 2002, pp. 15-22.
• [18] A. U. Ithalid, Z. Zilic, K. Radecka, FPGA emulation of quantum circuits, Proc. IEEE Int. Conference on Computer Design, 2004, pp. 310-315.
• [19] D. Maslov, G. Dueck, N. Scott, Reversible logic synthesis benchmarks page, http://www.cs.uvic.ca/-dmaslov/