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Warianty tytułu
Methods of Power Calculation in Digital Circuits
Konferencja
Reprogramowalne Układy Cyfrowe (18-19 maja 2006; Szczecin; Polska)
Języki publikacji
Abstrakty
Artykuł opisuje stan obecnych badań w dziedzinie metod obliczania mocy układów cyfrowych. Obliczanie (estymacja) mocy ma zasadnicze znaczenie podczas projektowania systemów cyfrowych o niskim poborze mocy. Przeprowadzono analizę technik stosowanych do obliczania mocy zarówno dla układów kombinacyjnych jak i sekwencyjnych na różnych poziomach abstrakcji, jak również metody mające zastosowanie do układów FPGA.
The state of contemporary researches in digital circuit power calculation was described in this paper. Power calculation (estimation) has great meaning during low power digital circuits designing. Analysis of techniques used in power calculating was made, either for combinational or sequential circuits on different levels of abstraction, as well as methods used for calculation of power in FPGA structures.
Wydawca
Czasopismo
Rocznik
Tom
Strony
101--102
Opis fizyczny
bibliogr. 14 poz.
Twórcy
Bibliografia
- [1] S. Flhanja, N. Ranganathan, Switching Activity Estimation of VLSI Circuits Using Bayesian Networks, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 4, 2003, pp. 558-567.
- [2] M. Eiermann, W. Stechele, RTL Power Modeling and Estimation Based on Bit and Word Level Switching Properties. In Proceedings of IEEE International Midwest Symposium on Circuits and Systems, 2002, Vol. 1, pp. I-144 - I-147.
- [3] A. T. Freitas, A. L. Oliveira: Implicit Resolution of the Chapman-Kotmogorov Equations for Sequential Circuits: An Application in Poer Estimation. In Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE) 2003, pp. 10764-10769.
- [4] S. Gupta, F. N. Najm: Analytical Models for RTL Power Estimation on Combinational and Sequential Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, Issue 7, 2000, pp. 808-814.
- [5] C.-Y. Hsu, W.-Z. Shen: Vector Compaction for Power Estimation with Grouping and Consecutive Sampling Techniques. In Proceedings of IEEE International Symposium on Circuits and Systems, 2002, pp. II-472 - II-475.
- [6] X Liu. M. C. Papaefthymiou: A Statistical Model of Input Glitch Propagation and Its Application in Power Macromodelling. In Proceedings of 45th IEEE International Midwest Symposium on Circuits and Systems, 2002, pp. 1-380-1-383.
- [7] X. Liu, M. C. Papaefthymiou: A Markov Chain Sequence Generator for Power Macromodeling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 7, 2004, pp. 1048-1062.
- [8] H. Y. Lui, C. H. Lee, R. H. Patel: Power Estimation ami Thermal Budgeting Methodology for FPGAs. In Proceedings of IEEE Custom Integrated Circuits Conference, 2004, pp. 32-1-1 - 32-1-4.
- [9] A. Macii, P.. Macii, M. Poncino, R. Scarsi: Stream Synthesis for Efficient Power Simulation Based on Spectral Transforms. IEHE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 3, 2001, pp. 417-426.
- [10] M. Pedram: Power simulation and estimation in VISI circuits. In "The VLSI Handhook", ed. W-K. Chen, The CRC Press and the IEEE Press 1999.
- [11] S. S. Ramani, S. Bhanja: Any-time Probabilistic Switching Model using Bayesian Networks. In Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), 2004, pp. 86-89.
- [12] C.-Y. Tsui. J. Monteiro, M. Pedram, S. Devadas. A. M. Despain, B. Lin: Power Estimation Methods for Sequential Logic Circuits. IEEE Transactions on VLSI Systems, Vol. 3. No. 3, 1995, pp. 404-416.
- [13] Altera Data Book, Altera Co., 1996.
- [14] The Programmable Gale Array Data Book, Xilinx Inc., 1991.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BSW4-0027-0034