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CLP approach to optimal instruction scheduling for VLIW processors

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Języki publikacji
EN
Abstrakty
EN
Along with modern processor architectures where multiple functional units can execute instructions in parallel and numerous resources have to be managed, there is a need for efficient tools facilitating code generation and enhancing development. The aim is to achieve maximal instruction throughput. This is a place where automatic optimization techniques should be employed due to high complexity of the real life problems. This article presents an approach to optimal instruction scheduling for very long instruction word (VLIW) processors using a constraint logic programming (CLP) solver with particular emphasis on the modulo scheduling technique. Modulo scheduling is an optimization technique used to achieve greater instruction level parallelism than one achievable by just optimally scheduling code basic blocks.
Rocznik
Strony
127--149
Opis fizyczny
Bibliogr. 8 poz., rys., tab.
Twórcy
  • Motorola Polska Electronics Sp. z o.o.
Bibliografia
  • [1] K. R. APT and M. G. WALLACE: Constraint logie programming using eclipse. Cambridge University Press, 2007.
  • [2] W. F. CLOCKSIN and CS. MELLISH: Programming in Prolog. Springer-Verlag, 1981.
  • [3] B. D. DE DINECHIN: Time-indexed formulations and a large neighborhood search for the resource-constrained modulo scheduling problem. Proc. 3rd Multidisci-plinary Int. Conf. on Scheduling: Theory and Applications, (2007).
  • [4] M. L. GINSBERG and W.D. HARVEY: Limited discrepancy search. Proc. 14th Int. Joint Conf. on Artificial Intelligence, (1995).
  • [5] B. R. RAU: Iterative modulo scheduling. HP Technical Report, Hewlett-Packard Laboratories. Pało Alto, Calif, USA, 1995.
  • [6] ILOG. CPLEX. www.ilog.com/products/cplex/, 2008.
  • [7] The ECL'PSe Constraint Programming System http://www.eclipse-clp.org/, 2008.
  • [8] ZGRYiewer http://zvtm.sourceforge.net/zgrviewer.html, 2008.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BSW3-0061-0007
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