Some quantum limits for scaling of electronic devices - estimations and measurements

• Autorzy: Nawrocki W. , Shukrinov Y. M.
• Języki publikacji: PL

Abstrakty

EN

In this paper we discuss some physical limits for scaling of transistors and conducting paths inside of semiconductor integrated circuits (ICs). Since 40 years only a semiconductor technology, mostly the CMOS and the TTL technologies, are used for fabrication of integrated circuits on an industrial scale. Miniaturization of electronic devices in integrated circuits has technological limits and physical limits as well. In 2010 best parameters of commercial ICs shown the Intel Core i5-670 processor manufactured in the technology of 32 nm. Its clock frequency in turbo mode is 3.73 GHz. A forecast of the development of the semiconductor industry (ITRS 2011) predicts that sizes of electronic devices in ICs circuits will be smaller than 10 nm in the next 10 years. At least 5 physical effects should be taken into account if we discuss limits of scaling of integrated circuits.

Słowa kluczowe

EN

nanostructure; quantum effect; integrated circuits

• Wydawca: Komitet Metrologii i Aparatury Naukowej PAN
• Czasopismo: Metrology and Measurement Systems
• Rocznik: 2012
• Tom: Vol. 19, nr 3
• Strony: 481--488
• Opis fizyczny: Bibliogr. 11 poz., rys., tab.

Twórcy

autor

Nawrocki W.

autor

Shukrinov Y. M.

• Poznan University of Technology, Faculty of Electronics and Telecommunications, ul. Piotrowo 3A, 60-965 Poznan, Poland,

Bibliografia

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