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Characteristics of an image sensor with early-vision processing fabricated in standard 0.35 žm CMOS technology

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Języki publikacji
PL
Abstrakty
EN
The article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 žm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image processing algorithms. The prototype with a resolution of 32 x 32 pixels allows the acquisition and processing of images at high speed, up to 2000 frames/s. Operation of the prototypes was verified in practice using the developed software and a measurement system based on a FPGA platform.
Rocznik
Strony
191--202
Opis fizyczny
Bibliogr. 27 poz., rys., tab., wykr.
Twórcy
autor
  • Gdansk University of Technology, Faculty of Electronics Telecommunications and Informatics, Department of Microelectronic Systems, Narutowicza 11/12, 80-233 Gdańsk, Poland, waldi@eti.pg.gda.pl
Bibliografia
  • [1] Cummings, E.R., Kalayjian, Z.K., Cai, D. (2001). A programmable focal plane MIMD image processor chip. IEEE J. Solid-State Circuits, 36(1), 64-73.
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  • [3] Schemmel, J., Meier, K., Loose, M. (2002). A scalable switched capacitor realization of the resistive fuse network. Analog Integrated Circui Signal Processing, 32, 135-148.
  • [4] Dupret, A., Klein, J.O., Nshare, A. (2002). A DSP-like analog processing unit for smart image sensors. Int. J. Circuit Theory Applicat., 30, 595-609.
  • [5] Dudek, P., Hicks, P.J., (2001). An Analogue SIMD Focal Plane Processor Array. In Proc. of IEEE Int. Symp. Circuits and Systems ISCAS 2001, IV, 490-493.
  • [6] Dudek, P., Hicks, P.J., (2005). A general-purpose processor-per-pixel analog SIMD vision chip. IEEE Trans. Circuits Syst. I: Regular papers, 52(1), 13-20.
  • [7] Nilchi, A., Aziz, J., Genov, R. (2009). Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor. IEEE J. Solid-State Circuits, 44(6), 1829-1839.
  • [8] Lopich, A., Dudek, P. (2011). A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities. IEEE Trans. Circuits Syst. I, 58(10), 2420-2431.
  • [9] Liñán Cembrano, G., Rodríguez-Vázquez, A., Carmona Galan, R., et al. (2004). A 1000 FPS at 128 × 128 vision processor with 8-bit digitized I/O. IEEE J. Solid-State Circuits, 39(7), 1044-1055.
  • [10] Dubois, J., Ginhac, D., Paindavoine, M., Heyrman, B. (2008). A 10 000 fps CMOS Sensor With Massively Parallel Image Processing. IEEE J. Solid-State Circuits, 43(3), 706-717.
  • [11] Higgins, Ch.M., Deutschmann, R.A., Koch, Ch. (1999). Pulse-based 2-D motion sensor. IEEE Trans. Circuits Syst. II, 46(6), 677-687.
  • [12] Gruev, V., Etienne-Cummings, R. (2002). Implementation of Steerable Spatiotemporal Image Filters on the Focal Plane. IEEE Trans. Circuits Syst. II, 49(4), 233-244.
  • [13] Massari, N., Gottardi, M., Gonzo, L., Stoppa, D., Simoni, A. (2005). A CMOS Image Sensor With Programmable Pixel-Level Analog Processing. IEEE Trans. Neural Netw., 16(6), 1673-1684.
  • [14] Takahashi, N., Fujita, K., Shibata, T. (2009). A Pixel-Parallel Self-Similitude Processing for Multiple-Resolution Edge-Filtering Analog Image Sensor. IEEE Trans. Circuits Syst. I, 56(11), 2384-2392.
  • [15] Elouardi, A., Bouaziz, S., Dupret, A., Lacassagne, L., Klein, J.O., Reynaud, R. (2007). Image Processing Vision Systems: Standard Image Sensors Versus Retinas. IEEE Trans. Instrum. Meas., 56(5), 1675-1687.
  • [16] Nilchi, A., Aziz, J., Genov, R. (2009). Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor. IEEE J. Solid-State Circuits, 44(6), 1829-1839.
  • [17] Lin, Z., Hoffman, M.W., Schemm, N., Leon-Salas, W.D., Balkir, S. (2008). A CMOS Image Sensor for Multi-Level Focal Plane Image Decomposition. IEEE Trans. Circuits Syst. I, 55(9), 2561-2572.
  • [18] Njuguna, R., Gruev, V. (2010). Linear Current Mode Image Sensor Width Focal Plane Spatial Image Processing. In Proc. IEEE Int. Symp. Circuits and Systems ISCAS 2010, 4, 4265-4268.
  • [19] Liñán Cembrano, G., Rodríguez-Vázquez, A., Carmona Galan, R., et al. (2004). A 1000 FPS at 128 × 128 vision processor with 8-bit digitized I/O. IEEE J. Solid-State Circuits, 39(7), 1044-1055.
  • [20] Gamal, A.E., Eltoukhy, H. (2005). CMOS image sensors. IEEE Circuits & Devices Magazine, 6-20.
  • [21] ELIS-1024 IMAGER. High Performance Image Sensors. Datasheet for Panavision Imaging. http://www.panavisionimaging.com/imagers_elis.htm.
  • [22] Dudek, P., Hicks, P.J. (2000). A CMOS general-purpose sampled-data analog processing element. IEEE Trans. Circuits Syst. II, 47(5), 467-473.
  • [23] Blakiewicz, G. (2009). Analog multiplier for a low-power integrated image sensor. In Proc. of 16th Int. Conf. Mixed Design of Integrated Circuits & Systems MIXDES’09, Łódź, Poland, 226-229.
  • [24] Jendernalik, W., Jakusz, J., Blakiewicz, G., Piotrowski, R., Szczepański, S. (2011). CMOS realisation of analogue processor for early vision processing. Bulletin of the Polish Academy of Sciences, Technical Sciences, 59(2), 141-147.
  • [25] Stevanovic, N., Hillebrand, M., Hosticka, B.J., Iurgel, U., Teuner, A. (1999). A High Speed Camera System Based on a Image Sensor in Standard CMOS Technology. In Proc. of IEEE Int. Symp. Circuits and Systems ISCAS’99, 5, 148-151.
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  • [27] Gryboś, P., Kmon, P., Żołądź, M., Szczygieł, R., Kachel, M., Lewandowski, M., Błasiak, T. (2011). 64 Channel Neural Recording Amplifier with Tunable Bandwidth in 180 nm CMOS Technology. Metrol. Meas. Syst., 18(4), 631-644.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-BSW1-0097-0002
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