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The article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 žm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image processing algorithms. The prototype with a resolution of 32 x 32 pixels allows the acquisition and processing of images at high speed, up to 2000 frames/s. Operation of the prototypes was verified in practice using the developed software and a measurement system based on a FPGA platform.
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Tom
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191--202
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Bibliogr. 27 poz., rys., tab., wykr.
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autor
autor
autor
autor
autor
- Gdansk University of Technology, Faculty of Electronics Telecommunications and Informatics, Department of Microelectronic Systems, Narutowicza 11/12, 80-233 Gdańsk, Poland, waldi@eti.pg.gda.pl
Bibliografia
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- [4] Dupret, A., Klein, J.O., Nshare, A. (2002). A DSP-like analog processing unit for smart image sensors. Int. J. Circuit Theory Applicat., 30, 595-609.
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- [6] Dudek, P., Hicks, P.J., (2005). A general-purpose processor-per-pixel analog SIMD vision chip. IEEE Trans. Circuits Syst. I: Regular papers, 52(1), 13-20.
- [7] Nilchi, A., Aziz, J., Genov, R. (2009). Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor. IEEE J. Solid-State Circuits, 44(6), 1829-1839.
- [8] Lopich, A., Dudek, P. (2011). A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities. IEEE Trans. Circuits Syst. I, 58(10), 2420-2431.
- [9] Liñán Cembrano, G., Rodríguez-Vázquez, A., Carmona Galan, R., et al. (2004). A 1000 FPS at 128 × 128 vision processor with 8-bit digitized I/O. IEEE J. Solid-State Circuits, 39(7), 1044-1055.
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- [12] Gruev, V., Etienne-Cummings, R. (2002). Implementation of Steerable Spatiotemporal Image Filters on the Focal Plane. IEEE Trans. Circuits Syst. II, 49(4), 233-244.
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- [16] Nilchi, A., Aziz, J., Genov, R. (2009). Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor. IEEE J. Solid-State Circuits, 44(6), 1829-1839.
- [17] Lin, Z., Hoffman, M.W., Schemm, N., Leon-Salas, W.D., Balkir, S. (2008). A CMOS Image Sensor for Multi-Level Focal Plane Image Decomposition. IEEE Trans. Circuits Syst. I, 55(9), 2561-2572.
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- [19] Liñán Cembrano, G., Rodríguez-Vázquez, A., Carmona Galan, R., et al. (2004). A 1000 FPS at 128 × 128 vision processor with 8-bit digitized I/O. IEEE J. Solid-State Circuits, 39(7), 1044-1055.
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- [22] Dudek, P., Hicks, P.J. (2000). A CMOS general-purpose sampled-data analog processing element. IEEE Trans. Circuits Syst. II, 47(5), 467-473.
- [23] Blakiewicz, G. (2009). Analog multiplier for a low-power integrated image sensor. In Proc. of 16th Int. Conf. Mixed Design of Integrated Circuits & Systems MIXDES’09, Łódź, Poland, 226-229.
- [24] Jendernalik, W., Jakusz, J., Blakiewicz, G., Piotrowski, R., Szczepański, S. (2011). CMOS realisation of analogue processor for early vision processing. Bulletin of the Polish Academy of Sciences, Technical Sciences, 59(2), 141-147.
- [25] Stevanovic, N., Hillebrand, M., Hosticka, B.J., Iurgel, U., Teuner, A. (1999). A High Speed Camera System Based on a Image Sensor in Standard CMOS Technology. In Proc. of IEEE Int. Symp. Circuits and Systems ISCAS’99, 5, 148-151.
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Bibliografia
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bwmeta1.element.baztech-article-BSW1-0097-0002